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pi7c9x111sl pci express-to-pci reversible bridge revision 1.5 3545 north 1 st street, san jose, ca 95134 phone: 1-877-pericom (1-877-737-4266) fax: 1-408-435-1100 internet: http://www.pericom.com
pi7c9x111sl pcie-to-pci reversible bridge page 2 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 life support policy pericom semiconductor corporation? s products are not authorized for use as criti cal components in life support devices or syste ms unless a specific written agreement pertaining to such intended use is ex ecuted between the manufacturer and an officer of psc. 1) life support devices or system are devices or systems which: a) are intended for surgical implant into the body or b) support or sustain life and w hose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2) a critical component is any component of a life support device or system whose failure to perf orm can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or e ffectiveness. pericom semiconductor corporation reserves the ri ght to make changes to its products or specifications at any time, without notice, in or der to improve design or performance and to supply the best po ssible product. pericom semiconductor does not assume any responsibility for use of any circ uitry described other than the circuitry embodied in a peri com semiconductor product. the company makes no representations that circuitry descri bed herein is free from patent infringement or other rights of third parties which may result from its use. no license is granted by implication or otherwise under an y patent, patent rights or other rights, of pericom semiconductor corporation. all other trademarks are of their respective companies.
pi7c9x111sl pcie-to-pci reversible bridge page 3 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 revision history date revision # description 10/18/2008 1.0 released version 1.0 datasheets 04/14/2009 1.1 revised general feature to reflect i-temp 10/10/2009 1.2 updated pin descrip tion of pci express signals 12/14/2009 1.3 updated pin descrip tion of power and ground pins 02/08/2009 1.4 updated section 10. 2 system management bus 02/22/2010 1.5 updated esd capability preface the datasheet of pi7c9x111sl will be enhanced periodically when updated information is available. the technical information in this datasheet is subject to change without notice. this document describes the functionalities of pi7c9x111sl (pci express bridge) and pr ovides technical information for designers to design their hardware using pi7c9x111sl.
pi7c9x111sl pcie-to-pci reversible bridge page 4 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 table of contents 1 introduction ................................................................................................................... ..... 10 1.1 pci express features................................................................................................... 10 1.2 pci features............................................................................................................... ...... 11 1.3 general features ........................................................................................................ 11 2 pin definitions................................................................................................................ ...... 12 2.1 signal types ............................................................................................................... ..... 12 2.2 pci express signals ...................................................................................................... 12 2.3 pci signals ................................................................................................................ ........ 12 2.4 mode select and strapping signals................................................................... 15 2.5 jtag boundary scan signals ................................................................................. 15 2.6 miscellaneous signals ............................................................................................. 15 2.7 power and ground pins............................................................................................. 15 2.8 pin assignments............................................................................................................ . 16 3 mode selection and pin strapping.......................................................................... 16 3.1 functional mode selection ................................................................................... 17 3.2 pin strapping .............................................................................................................. ..... 17 4 forward and reverse bridging................................................................................ 18 5 pci express functional overview........................................................................... 20 5.1 tlp structure.............................................................................................................. ... 20 5.2 virtual isochronous operation.......................................................................... 20 6 configuration register access............................................................................... 21 6.1 configuration register map.................................................................................. 21 6.2 pci express extended capa bility register map ........................................... 23 6.3 pci configuration registers.................................................................................. 25 6.3.1 vendor id ? of fset 00h ......................................................................................................... ....... 25 6.3.2 device id ? offset 00h......................................................................................................... ......... 25 6.3.3 command register ? offset 04h .............................................................................................. 25 6.3.4 primary status register ? offset 04h................................................................................... 26 6.3.5 revision id regist er ? offset 08h ........................................................................................... 27 6.3.6 class code regist er ? offset 08h ........................................................................................... 27 6.3.7 cache line size regi ster ? offset 0ch.................................................................................. 28 6.3.8 primary latency timer register ? offset 0ch .................................................................. 28 6.3.9 primary header type register ? offset 0ch ...................................................................... 28 6.3.10 reserved registers ? of fset 10h to 17h................................................................................ 28 6.3.11 primary bus number register ? offset 18h ........................................................................ 28 6.3.12 secondary bus number reg ister ? offset 18h .................................................................. 28 6.3.13 subordinate bus number register ? offset 18h .............................................................. 28 6.3.14 secondary latency time re gister ? offset 18h................................................................ 29 6.3.15 i/o base register ? offset 1ch................................................................................................. .29 6.3.16 i/o limit register ? offset 1ch................................................................................................ .29
pi7c9x111sl pcie-to-pci reversible bridge page 5 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 6.3.17 secondary status regist er ? offset 1ch ............................................................................ 29 6.3.18 memory base regist er ? offset 20h ....................................................................................... 30 6.3.19 memory limit regist er ? offset 20h ...................................................................................... 30 6.3.20 prefetchable memory base re gister ? offs et 24h......................................................... 30 6.3.21 prefetchable memory limit re gister ? offs et 24h........................................................ 31 6.3.22 prefetchable base upper 32-bit register ? offset 28h................................................. 32 6.3.23 prefetchable limit upper 32-bit register ? offset 2ch............................................... 32 6.3.24 i/o base upper 16-bit register ? offset 30h......................................................................... 32 6.3.25 i/o limit upper 16-bit re gister ? offset 30h........................................................................ 32 6.3.26 capability pointer ? offset 34h .............................................................................................. 32 6.3.27 expansion rom base address reg ister ? offset 38h ....................................................... 32 6.3.28 interrupt line register ? offset 3ch................................................................................... 32 6.3.29 interrupt pin register ? offset 3ch ..................................................................................... 33 6.3.30 bridge control register ? offset 3ch ................................................................................ 33 6.3.31 pci data buffering control register ? offset 40h ....................................................... 34 6.3.32 chip control 0 regist er ? offset 40h................................................................................... 35 6.3.33 reserved register ? offset 44h............................................................................................... 37 6.3.34 arbiter enable register ? offset 48h................................................................................... 37 6.3.35 arbiter mode register ? offset 48h...................................................................................... 37 6.3.36 arbiter priority regist er ? offset 48h ................................................................................ 38 6.3.37 reserved registers ? offset 4ch ............................................................................................ 38 6.3.38 memory readsmart base lower 32 -bit register 1 ? offset 50h.................................... 38 6.3.39 memory readsmart base upper 32-bit register 1 ? offset 54h .................................... 38 6.3.40 memory readsmart range control register 1 ? offset 58h ...................................... 39 6.3.41 memory readsmart base lower 32 -bit register 2 ? offset 5ch ................................... 39 6.3.42 memory readsmart base upper 32-bit register 2 ? offset 60h .................................... 39 6.3.43 memory readsmart range size register 2 ? offset 64h ................................................ 39 6.3.44 express transmitter/receiver register ? offset 68h.................................................... 39 6.3.45 upstream memory write fragment control register ? offset 68h ....................... 40 6.3.46 reserved register ? offset 6ch .............................................................................................. 41 6.3.47 eeprom autoload control/status register ? offset 70h........................................... 41 6.3.48 reserved register ? offset 74h............................................................................................... 42 6.3.49 gpio data and control register ? of fset 78h.................................................................. 42 6.3.50 reserved register ? offset 7ch .............................................................................................. 42 6.3.51 pci-x capability id regi ster ? offset 80h ............................................................................ 42 6.3.52 next capability pointer register ? offset 80h ................................................................ 42 6.3.53 pci-x secondary status re gister ? offset 80h.................................................................. 42 6.3.54 pci-x bridge status regi ster ? offset 84h.......................................................................... 43 6.3.55 upstream split transaction register ? offset 88h ........................................................ 43 6.3.56 downstream split transaction register ? offset 8ch ................................................. 44 6.3.57 power management id reg ister ? offs et 90h.................................................................... 44 6.3.58 next capability pointer register ? offset 90h ................................................................ 44 6.3.59 power management capability register ? offset 90h .................................................. 44 6.3.60 power management control and status register ? offset 94h .............................. 45 6.3.61 pci-to-pci support extension register ? offset 94h ..................................................... 45 6.3.62 reserved registers ? of fset 98h ? 9ch .................................................................................. 46 6.3.63 capability id register ? offset a0h....................................................................................... 46 6.3.64 next pointer register ? offset a0h....................................................................................... 46 6.3.65 slot number register ? offset a0h ....................................................................................... 46 6.3.66 chassis number regist er ? offset a0h ................................................................................. 46 6.3.67 secondary clock and clkrun cont rol register ? offset a4h................................. 46 6.3.68 capability id register ? offset a8h....................................................................................... 47
pi7c9x111sl pcie-to-pci reversible bridge page 6 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 6.3.69 next pointer register ? offset a8h....................................................................................... 47 6.3.70 reserved register ? offset a8h .............................................................................................. 48 6.3.71 subsystem vendor id register ? offset ach...................................................................... 48 6.3.72 subsystem id register ? offset ach ...................................................................................... 48 6.3.73 pci express capability id re gister ? offset b0h .............................................................. 48 6.3.74 next capability pointer re gister ? offset b0h ................................................................ 48 6.3.75 pci express capability regis ter ? offset b0h ................................................................... 48 6.3.76 device capability regi ster ? offset b4h............................................................................. 48 6.3.77 device control regist er ? offset b8h................................................................................. 50 6.3.78 device status register ? offset b8h..................................................................................... 50 6.3.79 link capability regist er ? offset bch ................................................................................. 51 6.3.80 link control register ? offset c0h...................................................................................... 51 6.3.81 link status register ? offset c0h.......................................................................................... 51 6.3.82 slot capability regist er ? offset c4h ................................................................................. 52 6.3.83 slot control register ? offset c8h ..................................................................................... 52 6.3.84 slot status register ? offset c8h ......................................................................................... 53 6.3.85 xpip configuration register 0 ? offset cch..................................................................... 53 6.3.86 xpip configuration register 1 ? offset d0h ..................................................................... 53 6.3.87 xpip configuration register 2 ? offset d4h ..................................................................... 53 6.3.88 l0 enter l1 waiting period counter ? offset d4h .......................................................... 55 6.3.89 capability id regist er ? offset d8h ...................................................................................... 55 6.3.90 next pointer register ? offset d8h ...................................................................................... 55 6.3.91 vpd register ? offset d8h ...................................................................................................... ... 55 6.3.92 vpd data register ? offset dch.............................................................................................. 55 6.3.93 reserved registers ? offset e0h ? ech ................................................................................. 56 6.3.94 message signaled interrupt s id regist er ? f0h............................................................... 56 6.3.95 next capabilities poin ter register ? f0h............................................................................ 56 6.3.96 message control register ? offset f0h ............................................................................. 56 6.3.97 message address register ? offset f4h .............................................................................. 56 6.3.98 message upper address regi ster ? offset f8h................................................................. 56 6.3.99 message data register ? offset fch..................................................................................... 57 6.3.100 advance error reporting capability id register ? offset 100h .............................. 57 6.3.101 advance error reporting capability ver sion register ? offset 100h .................. 57 6.3.102 next capability offset register ? offset 100h ................................................................ 57 6.3.103 uncorrectable error status register ? o ffset 104h ................................................... 57 6.3.104 uncorrectable error mask register ? offset 108h ...................................................... 57 6.3.105 uncorrectable error severity register ? offset 10ch............................................... 58 6.3.106 correctable error status re gister ? offs et 110h......................................................... 58 6.3.107 correctable error mask regi ster ? offset 114h ............................................................ 58 6.3.108 advanced error capabilities and control register ? offset 118h........................ 59 6.3.109 header log register 1 ? offset 11ch .................................................................................... 59 6.3.110 header log register 2 ? offset 120h..................................................................................... 59 6.3.111 header log register 3 ? offset 124h..................................................................................... 59 6.3.112 header log register 4 ? offset 128h..................................................................................... 59 6.3.113 secondary uncorrectable error status register ? offset 12ch ........................... 59 6.3.114 secondary uncorrectable error ma sk register ? offset 130h ............................... 60 6.3.115 secondary uncorrectable error severity register ? offset 134h ........................ 60 6.3.116 secondary error capability and control register ? offset 138h.......................... 61 6.3.117 secondary header log register ? offset 13ch ? 148h.................................................... 61 6.3.118 reserved register ? offset 14ch ............................................................................................ 61 6.3.119 vc capability id regis ter ? offset 150h ............................................................................... 61 6.3.120 vc capability version reg ister ? offset 150h ................................................................... 61
pi7c9x111sl pcie-to-pci reversible bridge page 7 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 6.3.121 next capability offset register ? offset 150h ................................................................ 62 6.3.122 port vc capability regist er 1 ? offset 154h ...................................................................... 62 6.3.123 port vc capability regist er 2 ? offset 158h ...................................................................... 62 6.3.124 port vc control register ? offset 15ch............................................................................. 62 6.3.125 port vc status register ? offset 15ch................................................................................. 62 6.3.126 vc0 resource capability re gister ? offset 160h ............................................................. 62 6.3.127 vc0 resource control reg ister ? offset 164h ................................................................. 62 6.3.128 vc0 resource status register ? offset 168h ..................................................................... 63 6.3.129 reserved registers ? of fset 16ch ? 300h .............................................................................. 63 6.3.130 extra gpi/gpo data and control register ? offset 304h............................................. 63 6.3.131 reserved registers ? of fset 308h ? 30ch .............................................................................. 63 6.3.132 replay and acknowledge latency timers ? offset 310h ............................................. 63 6.3.133 reserved registers ? of fset 314h ? ffch ............................................................................. 63 7 gpio pins and sm bus address....................................................................................... 64 8 clock scheme ................................................................................................................... .... 65 9 interrupts ..................................................................................................................... ......... 67 10 eeprom (i2c) interface and system management bus................................. 68 10.1 eeprom (i2c) interface ............................................................................................... 68 10.2 system management bus.......................................................................................... 68 10.3 eeprom autoload c onfiguration ....................................................................... 69 11 hot plug operation.......................................................................................................... 70 12 reset scheme................................................................................................................... ...... 71 13 ieee 1149.1 compatible jtag controller ............................................................. 72 13.1 instruction register.................................................................................................. 72 13.2 bypass register ............................................................................................................. 72 13.3 device id register ........................................................................................................ 73 13.4 boundary scan register.......................................................................................... 73 13.5 jtag boundary scan register order................................................................. 73 14 power management.......................................................................................................... 73 15 electrical and timing specifications ................................................................ 75 15.1 absolute maximum ratings ................................................................................... 75 15.2 dc specifications ......................................................................................................... . 75 15.3 ac specifications ......................................................................................................... . 76 16 package information ..................................................................................................... 77 17 ordering information ................................................................................................... 78
pi7c9x111sl pcie-to-pci reversible bridge page 8 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 table of figures f igure 1-1 pi7c9x111sl t opology ............................................................................................... 10 f igure 4-1 f orward b ridge m ode ..................................................................................................... 18 f igure 4-2 r everse b ridge m ode ....................................................................................................... 19 f igure 15-1 pci signal timing conditions ........................................................................................ 76 f igure 16-1 p ackage outline drawing ............................................................................................. 77 list of tables t able 2-1 p in a ssignments ................................................................................................................. 16 t able 3-1 m ode s election .................................................................................................................. 17 t able 3-2 p in s trapping ...................................................................................................................... 17 t able 4-1 tlp f ormat ......................................................................................................................... 20 t able 6-1 c onfiguration r egister m ap (00 h ? ff h )....................................................................... 21 t able 6-2 pci e xpress e xtended c apability r egister m ap (100 h ? fff h ) ................................. 24 t able 7-1 sm b us d evice id s trapping ............................................................................................ 64 t able 9-1 pci e interrupt message to pci interrupt mapping in reverse bridge mode ............. 68 t able 9-2 pci interrupt to pci e interrupt message mapping in forward bridge mode ............ 68 t able 13-1 i nstruction register codes ............................................................................................ 72 t able 13-2 jtag device id register ................................................................................................. 73 t able 15-1 a bsolute maximum ratings ............................................................................................ 75 t able 15-2 dc electrical characteristics ..................................................................................... 75 t able 15-3 pci bus timing parameters ............................................................................................. 76
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pi7c9x111sl pcie-to-pci reversible bridge page 10 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 1 introduction pi7c9x111sl is a pcie-to-pci/pci-x bridge. pi7c9x111sl is compliant with the pci express base specification, revision 1.1, the pci express card electromechanical specification , revision 1.1, the pci local bus specification, revision 3.0 and pci express to pci/pci-x bridge specification , revision 1.0. pi7c9x111sl supports transparent mode operation. also, pi7c9x111sl supports forward and reverse bridging. in forward bridge mode, pi7c9x111sl has an x1 pci express upstream port and a 32-bit pci downstream port. the 32-bit pci downstream port is 66mhz capable (see figure 1-1). in reverse bridge mode, pi7c9x111sl has a 32-bit pci upstream port and an x1 pci express downstream port. pi7c9x111sl configuration registers are backward compatible with existing pci bridge software and firmware . no modification of pci br idge software and firmware is needed for the original operation. figure 1-1 pi7c9x111sl topology 1.1 pci express features ? compliant with pci express base specification, revision 1.1 ? compliant with pci express card electro mechanical specification, revision 1.1 ? compliant with pci express to pci/pci-x bridge specification, revision 1.0 ? physical layer interface (x1 link with 2.5gb/s data rate) ? lane polarity toggle ? virtual isochronous support (upstream tc1-7 generation, downstream tc1-7 mapping) ? aspm support ? beacon support ? crc (16-bit), lcrc (32-bit) ? ecrc and advanced error reporting ? prbs (pseudo random bit sequencing) generator/checker for chip testing pi7c9x111sl x1 pci express port tx rx pci 32bit / 66mhz bus pci device pci device pci device pci device
pi7c9x111sl pcie-to-pci reversible bridge page 11 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 ? maximum payload size to 512 bytes 1.2 pci features ? compliant with pci local bus specification, revision 3.0 ? compliant with pci-to-pci bridge architecture specification, revision 1.2 ? compliant with pci bus pm inte rface specification, revision 1.1 ? compliant with pci hot-plug specification, revision 1.1 ? compliant with pci mobile design guide, version 1.1 ? 3.3v pci signaling with 5v i/o tolerance ? provides two level arbitration support for four pci bus masters ? 16-bit address decode for vga ? subsystem vendor and subsystem device ids support ? pci int interrupt or msi function support 1.3 general features ? compliant with advanced configuration and po wer interface specification (acpi), revision 2.0b ? compliant with system management (sm) bus, version 2.0 ? forward bridging (pci express as primary bus, pci as secondary bus) ? reverse bridging (pci as primary bus, pci express as secondary bus) ? transparent mode support ? gpio support (4 bi-directional pins) ? power management (including acpi, clkrun_l,clkreq_l, pci_pm) ? eeprom (i2c) interface ? sm bus interface ? auxiliary powers (vaux, vd daux, vddcaux) support ? power consumption less than 0.45 watt in typical condition ? industrial temperature range (-40c ~ +85c)
pi7c9x111sl pcie-to-pci reversible bridge page 12 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 2 pin definitions 2.1 signal types type of signal - descriptions b bi-directional i input iu input with pull-up id input with pull-down iod bi-directional with open drain output od open drain output o output p power g ground 2.2 pci express signals name pin assignment type description refclkp refclkn 7 9 i reference clock inputs: connect to external 100mhz differential clock. these signals require ac coupled with 0.1uf capacitors. rp rn 17 18 i pci express data inputs: differential data receiver input signals tp tn 14 13 o pci express data outputs: differential data transmitter output signals perst_l 36 i pci express fundamental reset: pi7c9x111sl uses this reset to initialize the internal state machines. 2.3 pci signals name pin assignment type description ad [31:0] 125, 123, 124, 121, 120, 119, 118, 116, 114, 113, 110, 109, 108, 107, 105, 104, 89, 87, 86, 85, 84, 83, 82, 80, 77, 76, 74, 73, 72, 71, 69, 68 b address / data: multiplexed address and data bus. address phase is aligned with first clock of frame_l assertion. data phase is aligned with irdy_l or trdy_l assertion. data is transferred on risi ng edges of clkout[0] when both irdy_l and trdy_l are asserted. during bus idle (both frame_l and irdy_l are de- asserted), pi7c9x111sl drives ad to a valid logic level when arbiter is parking to pi7c9x111sl on pci bus. cbe_l[3:0] 115, 102, 90, 79 b command / byte enables (active low): multiplexed command at address phase and byte enable at data phase. during a ddress phase, the initiator drives commands on cbe [3:0] signals to start the transaction. if the command is a write transaction, the initiator will drive the byte enables during data phase. otherwise, the target will drive the byte enables during data phase. duri ng bus idle, pi7c9x111sl drives cbe [3:0] signals to a valid logic level when arb iter is parking to pi7c9x111sl on pci bus. par 93 b parity bit: parity bit is an even parity (i.e. even number of 1?s), which generates based on the values of ad [31:0], cbe [3:0]. if pi7c9x111sl is an initiator with a write transaction, pi7c9x111sl will tri-stat e par. if pi7c9x111sl is a target and a write transaction, pi7c9x 111sl will drive par one clock after the address or data phase. if pi7c9x111sl is a target and a read transaction, pi7c9x111sl will drive par one clock after the address phase and tr i-state par during data phases. par is tri-stated one cycle after the ad lines ar e tri-stated. during bus idle, pi7c9x111sl drives par to a valid logic level when arbiter is parking to pi7c9x111sl on pci bus. frame_l 66 b frame (active low): driven by the initiator of a transaction to indicate the beginning and duration an access. the de-a ssertion of frame_l indicates the final data phase signaled by the initiator in burst transfers. before being tri-stated, it is driven to a de-asserted state for one cycle.
pi7c9x111sl pcie-to-pci reversible bridge page 13 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 name pin assignment type description irdy_l 99 b irdy (active low): driven by the initia tor of a transaction to indicate its ability to complete current data phase on the primary side. once asserted in a data phase, it is not de-asserted until the end of the data phase. before tri-stated, it is driven to a de- asserted state for one cycle. trdy_l 100 b trdy (active low): driven by the target of a tran saction to indicate its ability to complete current data phase on the primary side. once asserted in a data phase, it is not de-asserted until the end of the data phase . before tri-stated, it is driven to a de- asserted state for one cycle. devsel_l 98 b device select (active low): asserted by the target indicating that the device is accepting the transaction. as a master, pi 7c9x111sl waits for the assertion of this signal within 5 cycles of frame_l asser tion; otherwise, terminate with master abort. before tri-stated, it is driven to a de-asserted state for one cycle. stop_l 95 b stop (active low): asserted by the target indicating that the target is requesting the initiator to stop the current transaction. before tri-st ated, it is driven to a de- asserted state for one cycle. lock_l 96 b lock (active low): asserted by the initiator for multiple transactions to complete. pi7c9x111sl does not suppor t any upstream lock transaction. idsel 64 i initialization device select: used as a chip select line for type 0 configuration access to bridge?s configuration space. perr_l 92 b parity error (active low): asserted when a data parity error is detected for data received on the pci bus interface. before bei ng tri-stated, it is driven to a de-asserted state for one cycle. serr_l 63 iod system error (active low): can be driven low by any device to indicate a system error condition. if serr control is enabled, pi7c9x111sl will drive this pin on: address parity error posted write data par ity error on target bus master abort during posted write transaction target abort during posted write transaction posted write transaction discarded delayed write request discarded delayed read request discarded delayed transaction master timeout errors reported from pci express port (advanced error reporting) in transparent mode. this signal is an open drain buffer that requi res an external pull-up resistor for proper operation. req_l [3:0] 40, 38, 37, 35 i request (active low): req_l?s are asserted by bus master devices to request for transactions on the pci bus. the master de vices de-assert req_ls for at least 2 pci clock cycles before asserting them again. if external arbiter is selected, req_l [0] will be the bus grant input to pi7c9x111s l. also, req_l [3 :1] will become the gpi [2:0]. when powered up, if both req_l2 and req_l3 and pulled low (active low) and stay low in normal operation, the pi 7c9x111sl will change the function of clkout[3] to clkrun and clkout[2] to clkreq, respectively. gnt_l [3:0] 44, 43, 42, 41 o grant (active low): pi7c9x111sl asserts gnt_ls to release pci bus control to bus master devices. during idle and all gnt_l s are de-asserted and arbiter is parking to pi7c9x111sl, pi7c9x111sl will drive ad , cbe, and par to valid logic levels. if external arbiter is sel ected, gnt_l [0] will be the bus request from pi7c9x111sl to external arbiter. also, gnt_ l [3:1] will become the gpo [2:0]. clkout [3:0] 52,56,59,58 i/o pci clock outputs: pci clock outputs are derived from the clkin and provide clocking signals to external pci devices. in external feedback mode, clkout[0] becomes an input for feedback clock and clkout[1:3] remain as clock outputs to provide clock signals to external pc i devices. further detail on page 66. m66en 103 i 66mhz enable: this input is used to specify if bridge is capable of running at 66mhz. for 66mhz operation on the pci bus, th is signal should be pulled ?high?. for 33mhz operation on the pci bus, this signal should be pulled low. reset_l 49 b reset_l (active low): when reset_l active, all pci signals should be asynchronously tri-stated. inta_l intb_l intc_l intd_l 39 47 62 61 iod interrupt: signals are asserted to request an interrupt. after asserted, it can be cleared by the device driver. inta_l, intb_l, intc_l, intd_l signals are inputs and asynchronous to the clock in the forward mode. in reverse mode, inta_l, intb_l, intc_l, and intd_l are open dr ain buffers for sending interrupts to the host interrupt controller.
pi7c9x111sl pcie-to-pci reversible bridge page 14 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 name pin assignment type description clkin 48 i pci clock input: pci clock input signal connects to an external clock source. the pci clock outputs clkout [3:0] pi ns are derived from clkin input.
pi7c9x111sl pcie-to-pci reversible bridge page 15 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 2.4 mode select and strapping signals name pin assignment type description tm0 127 i mode select 0: mode selection pin to select eeprom or sm bus. tm0=0 for eeprom (i2c) support and tm0=1 for sm bus support. tm0 is also a strapping pin. see table 3-1 mode selecti on and 3-2 for strapping control. tm1 26 i mode select 1: mode selection pin for normal operation. set tm1=0 for normal operation. tm1=1 is reserved. msk_in 126 i hot plug enable input. revrsb 31 i forward or reverse bridging pin: revrsb pin controls the forward (revrsb=0) or reverse (revrsb=1) bridge mode of pi7c9x111sl. this pin is also a strapping pin. 2.5 jtag boundary scan signals name pin assignment type description tck 28 iu test clock: tck is the test clock to synchr onize the state information and data on the pci bus side of pi7c9x111sl during boundary scan operation. tms 27 iu test mode select: tms controls the state of the test access port (tap) controller. tdo 32 o test data output: tdo is the test data output and connects to the end of the jtag scan chain. tdi 29 iu test data input: tdi is the test data input and connects to the beginning of the jtag scan chain. it allows the test instructi ons and data to be serially shifted into the pci side of pi7c9x111sl. trst_l 30 iu test reset (active low): trst_l is the test reset to initialize the test access port (tap) controller. 2.6 miscellaneous signals name pin assignment type description gpio [3:0] 50, 51, 54, 55 b general purpose i/o data pins: the 4 general-purpose signals are programmable as either input-only or bi-directional signals by writing the gpio output enable control register in the configuration space. smbclk / scl 3 b smbus / eeprom clock pin: when eeprom (i2c) interface is selected (tm0=0), this pin is an output of scl cl ock and connected to eeprom clock input. when smbus interface is select ed (tm0=1), this pin is an input for the clock of smbus. smbdata / sda 4 b/iod smbus / eeprom data pin: data interface pin to eerpom or smbus. when eeprom (i2c) interface is selected (tm0=0), this pin is a bi-directional signal. when smbus interface is selected (tm0=1 ), this pin is an open drain signal. pme_l 1 b power management event pin: power management event signal is asserted to request a change in the device or link power state. 2.7 power and ground pins name pin assignment type description vdda 8, 20, 21 p analog voltage supply for pci express interface: connect to the 1.0v power supply. vddp 11, 23, 24 p digital voltage supply for pci express interface: connect to the 1.0v power supply. vddaux 15 p auxiliary voltage supply for pci express interface: connect to the 1.0v power supply. vtt 12 p termination supply voltage for pci express interface: connect to the 1.5v power supply. vddc 45, 65, 75, 94, 112 p core supply voltage: connect to the 1.0v power supply. vddcaux 5 p auxiliary core supply voltage: connect to the 1.0v power supply. vd33 33, 53, 60, 70, 81, 91, 101, 111, 122 p i/o supply voltage for pci interface: connect to the 3.3v power supply for pci i/o buffers.
pi7c9x111sl pcie-to-pci reversible bridge page 16 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 name pin assignment type description vaux 2 p auxiliary i/o supply volt age for pci interface: connect to the 3.3v power supply. vss 6, 10, 16, 19, 22, 25, 34, 46, 57, 67, 78, 88, 97, 106, 117, 128 p ground: connect to ground. 2.8 pin assignments table 2-1 pin assignments pin name pin name pin name pin name 1 pme_l 33 vd33 65 vddc 97 vss 2 vaux 34 vss 66 frame_l 98 devsel_l 3 smbclk / scl 35 req_l[0] 67 vss 99 irdy_l 4 smdat / sda 36 perst_l 68 ad[0] 100 trdy_l 5 vddcaux 37 req_l[1] 69 ad[1] 101 vd33 6 vss 38 req_l[2] 70 vd33 102 cbe_l[2] 7 refclkp 39 inta_l 71 ad[2] 103 m66en 8 vdda 40 req_l[3] 72 ad[3] 104 ad[16] 9 refclkn 41 gnt_l[0] 73 ad[4] 105 ad[17] 10 vss 42 gnt_l[1] 74 ad[5] 106 vss 11 vddp 43 gnt_l[2] 75 vddc 107 ad[18] 12 vtt 44 gnt_l[3] 76 ad[6] 108 ad[19] 13 txn 45 vddc 77 ad[7] 109 ad[20] 14 txp 46 vss 78 vss 110 ad[21] 15 vddaux 47 intb_l 79 cbe[0] 111 vd33 16 vss 48 clkin 80 ad[8] 112 vddc 17 rxp 49 reset_l 81 vd33 113 ad[22] 18 rxn 50 gpio[3] 82 ad[9] 114 ad[23] 19 vss 51 gpio[2] 83 ad[10] 115 cbe_l[3] 20 vdda 52 clkout[3] 84 ad[11] 116 ad[24] 21 vdda 53 vd33 85 ad[12] 117 vss 22 vss 54 gpio[1] 86 ad[13] 118 ad[25] 23 vddp 55 gpio[0] 87 ad[14] 119 ad[26] 24 vddp 56 clkout[2] 88 vss 120 ad[27] 25 vss 57 vss 89 ad[15] 121 ad[28] 26 tm1 58 clkout[0] 90 cbe_l[1] 122 vd33 27 tms 59 clkout[1] 91 vd33 123 ad[30] 28 tck 60 vd33 92 perr_l 124 ad[29] 29 tdi 61 intd_l 93 par 125 ad[31] 30 trst_l 62 intc_l 94 vddc 126 msk_in 31 revrsb 63 serr_l 95 stop_l 127 tm0 32 tdo 64 idsel 96 lock_l 128 vss 3 mode selection and pin strapping
pi7c9x111sl pcie-to-pci reversible bridge page 17 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 3.1 functional mode selection pi7c9x111sl uses tm1, tm0, and revrsb pins to select different modes of operations. these three input signals are required to be stable during normal operation. one of the eight combinati ons of normal operation can be selected by setting the logic values for the three mode select pins. for example, if the logic values are low for all three (tm1, tm0, and revrsb) pins, the normal ope ration will have eeprom (i2c) support with internal arbiter in forward bridge mode. the designated opera tion with respect to the values of the tm1, tm0, and revrsb pins are defined on table 3-1: table 3-1 mode selection tm1 tm0 revrsb functional mode 0 0 x eeprom (i2c) support 0 1 x sm bus support 0 x 0 forward bridge mode 0 x 1 reverse bridge mode 3.2 pin strapping if tm1 is strapped to low, pi7c9x111sl uses req_l[3:2], revrsb as the strapping pins at the pcie perst# de-assertion to enable clock power management feature. table 3-2 pin strapping tm1 strapped req_l[3:2] revrsb strapped test functions 0 2?b0 0 clock power management is enabled, only two pci devices supported. clkout[2] is used as clkreq# clkout[3] is used as clkrun# if tm1 is strapped to high, pi7c9x111sl uses tm0, revrsb as the strapping pins at the pcie perst# de- assertion transition in forw ard bridge mode or pci reset# de-asser tion transition in reverse bridge mode. tm1 strapped tm0 strapped revrsb strapped test functions 1 1 x short initialization 1 0 1 functional loopback test 1 0 0 bridge test (prbs, iddq, etc..)
pi7c9x111sl pcie-to-pci reversible bridge page 18 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 4 forward and reverse bridging pi7c9x111sl supports forward or reverse combination modes of operation. for example, when pi7c9x111sl is operating in forward pcie bridge (rev rsb=0), its pci express interface is connected to a root complex and its pci bus interface is connected to pci devices. another example, pi7c9x111sl can be configured as a reverse pcie bridge (revrsb=1). pci based systems and peripherals are ubiquitous in the i/ o interconnect technology market today. it will be a tremendous effort to convert existing pci based products to be used in pci express systems. pi7c9x111sl provides a solution to bridge existing pci based products to the latest pci express technology. figure 4-1 forward bridge mode in reverse mode (revrsb=1), pi7c9x111sl becomes a pci-to-pci express bridge that its pci bus interface is connected to the pci host chipset betwee n and the pci express x1 link. it enables the legacy pci host systems to provide pci express interface capability. pi7c9x111sl provides a solution to convert existing pci based designs to adapt quickly into pci express base platforms. existing pci based applications will not have to undergo a comp lete re-architecture in order to interface to pci express technology. pi7c9x111sl fibre channel root complex fast ethernet scsi hdd host processor system memory x1 link pci 32bit / 66mhz usb / 1394
pi7c9x111sl pcie-to-pci reversible bridge page 19 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 figure 4-2 reverse bridge mode pi7c9x111sl fibre channel host pci chipset fast ethernet scsi hdd host processor system memory pci 32bit / 66mhz x1 link
pi7c9x111sl pcie-to-pci reversible bridge page 20 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 5 pci express functional overview 5.1 tlp structure pci express tlp (transaction layer packet) structure is co mprised of format, type, traf fic class, attributes, tlp digest, tlp poison, and length of data payload. there are four tlp formats defined in pi7c9x111sl based on the states of fmt [1] and fmt [0] as shown on table 4-1. table 4-1 tlp format fmt [1] fmt [0] tlp format 0 0 3 double word, without data 0 1 4 double word, without data 1 0 3 double word, with data 1 1 4 double word, with data data payload of pi7c9x111sl can range from 4 (1dw) to 256 (64dw) bytes. pi7c9x111sl supports three tlp routing mechanisms. they are comprise d of address, id, and implicit routings. address routing is being used for memory and io requests. id based (bus, device, function numbers) routing is being used for configuration requests. implicit routing is being used for message routing. there are two message groups (baseline and advanced switching). the baseline message group contains intx interrupt signaling, power management, error signaling, locked transaction support, slot power limit support, vendor defined messages, hot-plug signaling. the other is advanced switching support message group. the advanced switching support message contains data packet and signal packet messages. advanced switching is beyond the scope of pi7c9x111sl implementation. the r [2:0] values of the "type" field will determine the destination of the message to be routed. all baseline messages must use the default traffic class zero (tc0). 5.2 virtual isochronous operation this section provides a summary of virtual isochronous operation supported by pi7c9x111sl. virtual isochronous support is disabled by default. virtual isoc hronous feature can be turned on with setting bit [26] of offset 40h to one. control bits are designated for selecting which traffic class (tc1-7) to be used for upstream (pci express-to-pci). pi7c 9x111sl accepts only tc0 packets of config uration, io, and message packets for downstream (pci express-to-pci). if configuration, io and message packets have traffic class other than tc0, pi7c9x111sl will treat them as malf ormed packets. pi7c9x111sl maps all downstream memory packets from pci express to pci transactions regardless the virtual isochronous operation is enabled or not.
pi7c9x111sl pcie-to-pci reversible bridge page 21 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 6 configuration register access pi7c9x111sl supports type-0 and ty pe-1 configuration space headers and capability id of 01h (pci power management) to 10h (pci express capability structure). with pin revrsb = 0, device-port type (bit [7:4]) of capab ility register will be set to 7h (pci expres s-to-pci). when pin revrsb = 1, device-port type (bit [7:4]) of ca pability register will be set to 8h (pci-to-pci express bridge). pi7c9x111sl supports pci express capabilities register st ructure with capability version set to 1h (bit [3:0] of offset 02h). 6.1 configuration register map pi7c9x111sl supports capability pointer with pci power management (id=01h), pci bridge sub-system vendor id (id=0dh), pci express (id=10h), vital product data (id=03h), and message signaled interrupt (id=05h). slot identification (id=04h) is off by default and can be turned on through configuration programming. table 6-1 configuration register map (00h ? ffh) primary bus configuration access or secondary bus configuration access pci configuration register name (type1) eeprom (i2c) access sm bus access 01h - 00h vendor id yes1 yes2 03h ? 02h device id yes1 yes2 05h ? 04h command register yes yes 07h ? 06h primary status register yes yes 0bh ? 08h class code and revision id yes1 yes2 0ch cacheline size register yes yes 0dh primary latency timer yes yes 0eh header type register yes yes 0fh reserved - - 17h ? 10h reserved - - 18h primary bus number register yes yes 19h secondary bus number register yes yes 1ah subordinate bus number register yes yes 1bh secondary latency timer yes yes 1ch i/o base register yes yes 1dh i/o limit register yes yes 1fh ? 1eh secondary status register yes yes 21h ? 20h memory base register yes yes 23h ? 22h memory limit register yes yes 25h ? 24h prefetchable memory base register yes yes 27h ? 26h prefetchable memory limit register yes yes 2bh ? 28h prefetchable memor y yes yes
pi7c9x111sl pcie-to-pci reversible bridge page 22 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 primary bus configuration access or secondary bus configuration access pci configuration register name (type1) eeprom (i2c) access sm bus access base upper 32-bit register 2dh ? 2ch prefetchable memory limit upper 32-bit register yes yes 2fh ? 2eh prefetchable memory limit upper 32-bit register yes yes 31h ? 30h i/o base upper 16-bit register yes yes 33h ? 32h i/o limit upper 16-bit register yes yes 34h capability pointer yes yes 37h ? 35h reserved no yes 3bh ? 38h reserved no yes 3ch interrupt line yes yes 3dh interrupt pin yes yes 3eh bridge control yes yes 3fh bridge control yes yes 41h ? 40h pci data prefetching control yes yes 43h ? 42h chip control 0 yes yes 45h ? 44h reserved - - 47h ? 46h reserved - - 4bh ? 48h arbiter mode, enable, priority - - 4ch reserved - - 4dh reserved - - 4eh reserved - - 4fh reserved - - 53h ? 50h reserved - - 57h ? 54h reserved - - 5bh ? 58h reserved - - 5fh ? 5ch reserved - - 63h ? 60h reserved - - 67h ? 64h reserved - - 69h ? 68h pci express tx and rx control yes yes 6ah reserved - - 6bh upstream memory write/read control yes yes 6dh ? 6ch reserved - - 6fh ? 6eh reserved - - 73h ? 70h eeprom (i2c) control and status register no yes 77h ? 74h reserved - - 7bh ? 78h gpio data and control yes yes 7ch reserved - - 7dh reserved - - 7eh reserved - - 7fh reserved - - 83h ? 80h pci-x capability yes yes 87h ? 84h pci-x bridge status yes yes 8bh ? 88h upstream split transaction yes yes 8fh ? 8ch downstream s p lit yes yes
pi7c9x111sl pcie-to-pci reversible bridge page 23 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 primary bus configuration access or secondary bus configuration access pci configuration register name (type1) eeprom (i2c) access sm bus access transaction 93h ? 90h power management capability yes yes 97h ? 94h power management control and status yes yes 9bh ? 98h reserved - - 9fh ? 9ch reserved - - a3h ? a0h slot id capability yes yes a7h ? a4h secondary clock and clkrun control yes yes abh ? a8h ssid and ssvid capability yes yes afh ? ach subsystem id and subsystem vendor id yes yes b3h ? b0h pci express capability yes yes b7h ? b4h device capability yes yes bbh ? b8h device control and status yes yes bfh ? bch link capability yes yes c3h ? c0h link control and status yes yes c7h ? c4h slot capability yes yes cbh ? c8h slot control and status yes yes cfh ? cch xpip configuration register 0 yes yes d3h ? d0h xpip configuration register 1 yes yes d6h ? d4h xpip configuration register 2 yes yes d7h hot swap switch debounce count yes yes dbh ? d8h vpd capability register yes yes dfh ? dch vpd data register yes3 yes e3h ? e0h extended config access address yes yes e7h ? e4h extended config access data yes yes ebh ? e8h reserved - - efh ? ech reserved - - f3h ? f0h msi capability register yes yes f7h ? f4h message address yes yes fbh ? f8h message upper address yes yes ffh ? fch message date yes yes note 1: when masquerade is enabled, it is pre-loadable. note 2: the vpd data is read/write through i2c during vpd operation. note 3: read access only. 6.2 pci express extended capability register map pi7c9x111sl also supports pci express extended capabilities with from 257-byte to 4096-byte space. the offset range is from 100h to fffh. the offset 100h is defined for advance error reporting (id=0001h). the offset 150h is defined for virtual channel (id=0002h).
pi7c9x111sl pcie-to-pci reversible bridge page 24 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 table 6-2 pci express extended capa bility register map (100h ? fffh) primary bus configuration access or secondary bus configuration access transparent mode (type1) eeprom (i2c) access sm bus access 103h ? 100h advanced error reporting (aer) capability yes yes2 107h ? 104h uncorrectable error status no yes 10bh ? 108h uncorrectable error mask yes yes 10fh ? 10ch uncorrectable severity no yes 113h ? 110h correctable error status no yes 117h ? 114h correctable error mask no yes 11bh ? 118h aer control no yes 12bh ? 11ch header log register no yes 12fh ? 12ch secondary uncorrectable error status no yes 133h ? 130h secondary uncorrectable error mask no yes 137h ? 134h secondary uncorrectable severity no yes 13bh ? 138h secondary aer control no yes 14bh ? 13ch secondary header log register no yes 14fh ? 14ch reserved no yes 153h ? 150h vc capability no yes 157h ? 154h port vc capability 1 no yes 15bh ? 158h port vc capability 2 no yes 15fh ? 15ch port vc status and control no yes 163h ? 160h vc0 resource capability no yes 167h ? 164h vc0 resource control no yes 16bh ? 168h vc0 resource status no yes 2ffh ? 170h reserved no no 303h ? 300h extended gpio data and control no yes 307h ? 304h extended gpi/gpo data and control no yes 30fh ? 308h reserved no no 310h replay and acknowledge latency timer yes yes 4ffh ? 314h reserved no no 503h ? 500h reserved no no 504h reserved no no 50fh ? 505h reserved no no 510h reserved no no fffh ? 514h reserved no no note 5: read access only.
pi7c9x111sl pcie-to-pci reversible bridge page 25 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 6.3 pci configuration registers the following section describes the conf iguration space when the device is in transparent mode. the descriptions for different register type are listed as follow: register type descriptions ro read only ros read only and sticky rw read/write rwc read/write ?1? to clear rws read/write and sticky rwcs read/write ?1? to clear and sticky 6.3.1 vendor id ? offset 00h bit function type description 15:0 vendor id ro identifies pericom as the vendor of this device. returns 12d8h when read. 6.3.2 device id ? offset 00h bit function type description 31:16 device id ro identifies this device as the pi7c9x111sl. returns e111 when read. 6.3.3 command register ? offset 04h bit function type description 0 i/o space enable rw 0: ignore i/ o transactions on the primary interface 1: enable response to memory tr ansactions on the primary interface reset to 0 1 memory space enable rw 0: ignore memory read transactions on the primary interface 1: enable memory read tran sactions on the primary interface reset to 0 2 bus master enable rw 0: do not initiate memo ry or i/o transactions on the primary interface and disable response to memory and i/o tr ansactions on the secondary interface 1: enable the bridge to operate as a master on the primary interfaces for memory and i/o transactions forwar ded from the secondary interface. reset to 0 3 special cycle enable ro 0: pi7c9x111sl does not respond as a target to special cycle transactions, so this bit is defined as read-only and must return 0 when read reset to 0 4 memory write and invalidate enable ro 0: pi7c9x111sl does not originate a memory write and invalidate transaction. implements this bit as read-only and returns 0 when read (unless forwarding a transaction for another master). reset to 0 5 vga palette snoop enable ro / rw this bit applies to reverse bridge only. 0: ignore vga palette access on the primary 1: enable positive decoding response to vga palette writes on the primary interface with i/o address bits ad [9 :0] equal to 3c6h, 3c8h, and 3c9h (inclusive of isa alias; ad [15:0] ar e not decoded and may be any value) reset to 0
pi7c9x111sl pcie-to-pci reversible bridge page 26 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 bit function type description 6 parity error response enable rw 0: may ignore any parity error that is detected and take its normal action 1: this bit if set, enables the setting of master data par ity error bit in the status register when poisoned tlp received or parity error is detected and takes its normal action reset to 0 7 wait cycle control ro wait cycle control not supported reset to 0 8 serr_l enable bit rw 0: disable 1: enable pi7c9x111sl in forward bri dge mode to report non-fatal or fatal error message to the root complex. also , in reverse bridge mode to assert serr_l on the primary interface reset to 0 9 fast back-to-back enable ro fast back-to-back enable not supported reset to 0 10 interrupt disable rw this bit applies to reverse bridge only. 0: inta_l can be asserted on pci interface 1: prevent inta_l from being asserted on pci interface reset to 0 15:11 reserved ro reset to 00000 6.3.4 primary status register ? offset 04h bit function type description 18:16 reserved ro reset to 000 19 reserved ro reset to 0 20 capability list capable ro 1: pi7c9x111sl supports the capability list (offset 34 h in the pointer to the data structure) reset to 1 21 66mhz capable ro this bit applies to reverse bridge only. 1: 66mhz capable reset to 0 when forward bridge or 1 when reverse bridge. 22 reserved ro reset to 0 23 fast back-to-back capable ro this bit applies to reverse bridge only. 1: enable fast back-to-back transactions reset to 0 when forward bridge or 1 when reverse bridge in pci mode. 24 master data parity error detected rwc bit set if its parity erro r enable bit is set and eith er of the conditions occurs on the primary: forward bridge ? receives a completion marked poisoned poisons a write request reverse bridge ? detected parity error when receivi ng data or split response for read observes p_perr_l asserted when se nding data or receiving split response for write receives a split completion message indicating data parity error occurred for non-posted write reset to 0
pi7c9x111sl pcie-to-pci reversible bridge page 27 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 bit function type description 26:25 devsel_l timing (medium decode) ro these bits apply to reverse bridge only. 00: fast devsel_l decoding 01: medium devsel_l decoding 10: slow devsel_l decoding 11: reserved reset to 00 when forward bridge or 01 when reverse bridge. 27 signaled target abort rwc forward bridge ? this bit is set when pi7c9x111sl completes a request using completer abort status on the primary reverse bridge ? this bit is set to indicate a target abort on the primary reset to 0 28 received target abort rwc forward bridge ? this bit is set when pi7c9x111sl receives a completion with completer abort completion status on the primary reverse bridge ? this bit is set when pi7c9x111sl de tects a target abort on the primary reset to 0 29 received master abort rwc forward bridge ? this bit is set when pi7c9x111sl receives a completion with unsupported request completion status on the primary reverse bridge ? this bit is set when pi7c9x111sl detects a master abort on the primary 30 signaled system error rwc forward bridge ? this bit is set when pi7c9x111sl sends an err_fatal or err_non_fatal message on the primary reverse bridge ? this bit is set when pi7c9x111sl asserts serr_l on the primary reset to 0 31 detected parity error rwc forward bridge ? this bit is set when poisoned tlp is detected on the primary reverse bridge ? this bit is set when address or data parity error is detected on the primary reset to 0 6.3.5 revision id register ? offset 08h bit function type description 7:0 revision ro reset to 00000002h 6.3.6 class code register ? offset 08h bit function type description 15:8 programming interface ro subtractive d ecoding of pci-pci br idge not supported reset to 00000000 23:16 sub-class code ro sub-class code 00000100: pci-to-pci bridge reset to 00000100 31:24 base class code ro base class code 00000110: bridge device reset to 00000110
pi7c9x111sl pcie-to-pci reversible bridge page 28 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 6.3.7 cache line size register ? offset 0ch bit function type description 1:0 reserved ro bit [1:0] not supported reset to 00 2 cache line size rw 1: cache line size = 4 double words reset to 0 3 cache line size rw 1: cache line size = 8 double words reset to 0 4 cache line size rw 1: cache line size = 16 double words reset to 0 5 cache line size rw 1: cache line size = 32 double words reset to 0 7:6 reserved ro bit [7:6] not supported reset to 00 6.3.8 primary latency timer register ? offset 0ch bit function type description 15:8 primary latency timer ro / rw 8 bits of primary latency timer in pci bus forward bridge ? ro with reset to 00h reverse bridge ? rw with reset to 00h in pci mode 6.3.9 primary header type register ? offset 0ch bit function type description 22:16 pci-to-pci bridge configuration ro ro pci-to-pci bridge configuration (10 ? 3fh) reset to 0000001 23 single function device ro 0: indicates single function device reset to 0 31:24 reserved ro reset to 00h 6.3.10 reserved registers ? offset 10h to 17h 6.3.11 primary bus number register ? offset 18h bit function type description 7:0 primary bus number rw reset to 00h 6.3.12 secondary bus number register ? offset 18h bit function type description 15:8 secondary bus number rw reset to 00h 6.3.13 subordinate bus number register ? offset 18h bit function type description
pi7c9x111sl pcie-to-pci reversible bridge page 29 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 bit function type description 23:16 subordinate bus number rw reset to 00h 6.3.14 secondary latency time register ? offset 18h bit function type description 31:24 secondary latency timer rw / ro secondary latency timer in pci bus forward bridge ? rw with reset to 00h in pci mode reverse bridge ? ro with reset to 00h 6.3.15 i/o base register ? offset 1ch bit function type description 1:0 32-bit i/o addressing support ro 01: indicates pi7c9x111sl supports 32-bit i/o addressing reset to 01 3:2 reserved ro reset to 00 7:4 i/o base rw indicates the i/o base (0000_0000h) reset to 0000 6.3.16 i/o limit register ? offset 1ch bit function type description 9:8 32-bit i/o addressing support ro 01: indicates pi7c9x111sl supports 32-bit i/o addressing reset to 01 11:10 reserved ro reset to 00 15:12 i/o base rw indicates the i/o limit (0000_0fffh) reset to 0000 6.3.17 secondary status register ? offset 1ch bit function type description 20:16 reserved ro reset to 00000 21 66mhz capable ro indicates pi7c9x111sl is 66mhz capable reset to 1 22 reserved ro reset to 0 23 fast back-to-back capable ro forward bridge: reset to 1 when secondary bus is in pci mode (supports fast back-to-back transactions) reverse bridge: reset to 0 (does not support fast back-to-back transactions) 24 master data parity error detected rwc this bit is set if its pa rity error enable bit is set and either of the conditions occur on the primary: forward bridge ? ? detected parity error when receivi ng data or split response for read ? observes s_perr_l asserted when sending data or receiving split response for write ? receives a split completion message indicating data parity error occurred for non-posted write reverse bridge ? ? receives a completion marked poisoned ? poisons a write request reset to 0
pi7c9x111sl pcie-to-pci reversible bridge page 30 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 bit function type description 26:25 devsel_l timing (medium decoding) ro these bits apply to forward bridge only. 01: medium devsel_l decoding reset to 01 when forward mode or 00 when reverse mode. 27 signaled target abort rwc forward bridge ? bit is set when pi7c9x111sl signals target abort reverse bridge ? bit is set when pi7c9x111sl complete s a request using completer abort completion status reset to 0 28 received target abort rwc forward bridge ? bit is set when pi7c9x111sl detects ta rget abort on the secondary interface reverse bridge ? bit is set when pi7c9x111sl receives a completion with completer abort completion status on the secondary interface reset to 0 29 received master abort rwc forward bridge ? bit is set when pi7c9x111sl detects master abort on the secondary interface reverse bridge ? bit is set when pi7c9x111sl receives a completion with unsupported request completion status on the primary interface reset to 0 30 received system error rwc forward bridge ? bit is set when pi7c9x111sl detect s serr_l assertion on the secondary interface reverse bridge ? bit is set when pi7c9x111sl receives an err_fatal or err_non_fatal message on the secondary interface reset to 0 31 detected parity error rwc forward bridge ? bit is set when pi7c9x111sl detect s address or data parity error reverse bridge ? bit is set when pi7c9x111sl detects poisoned tlp on secondary interface reset to 0 6.3.18 memory base register ? offset 20h bit function type description 3:0 reserved ro reset to 0000 15:4 memory base rw memory base (80000000h) reset to 800h 6.3.19 memory limit register ? offset 20h bit function type description 19:16 reserved ro reset to 0000 31:20 memory limit rw memory limit (000fffffh) reset to 000h 6.3.20 prefetchable memory base register ? offset 24h bit function type description
pi7c9x111sl pcie-to-pci reversible bridge page 31 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 bit function type description 3:0 64-bit addressing support ro 0001: indi cates pi7c9x111sl supports 64-bit addressing reset to 0001 15:4 prefetchable memory base rw prefetchable memory base (00000000_80000000h) reset to 800h 6.3.21 prefetchable memory limit register ? offset 24h bit function type description 19:16 64-bit addressing support ro 0001: indi cates pi7c9x111sl supports 64-bit addressing reset to 0001 31:20 prefetchable memory limit rw pr efetchable memory limit (00000000_000fffffh) reset to 000h
pi7c9x111sl pcie-to-pci reversible bridge page 32 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 6.3.22 prefetchable base upper 32-bit register ? offset 28h bit function type description 31:0 prefetchable base upper 32- bit rw bit [63:32] of prefetchable base reset to 00000000h 6.3.23 prefetchable limit upper 32-bit register ? offset 2ch bit function type description 31:0 prefetchable limit upper 32-bit rw bit [63:32] of prefetchable limit reset to 00000000h 6.3.24 i/o base upper 16-bit register ? offset 30h bit function type description 15:0 i/o base upper 16-bit rw bit [31:16] of i/o base reset to 0000h 6.3.25 i/o limit upper 16-bit register ? offset 30h bit function type description 31:16 i/o limit upper 16-bit rw bit [31:16] of i/o limit reset to 0000h 6.3.26 capability pointer ? offset 34h bit function type description 31:8 reserved ro reset to 0 7:0 capability pointer ro capability pointer to 80h reset to 80h 6.3.27 expansion rom base address register ? offset 38h bit function type description 31:0 expansion rom base address ro expansion rom not supported. reset to 00000000h 6.3.28 interrupt line register ? offset 3ch bit function type description 7:0 interrupt line rw for initialization code to program to tell which input of the interrupt controller the pi7c9x111sl?s inta_l in connected to. reset to 00000000
pi7c9x111sl pcie-to-pci reversible bridge page 33 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 6.3.29 interrupt pin register ? offset 3ch bit function type description 15:8 interrupt pin ro designates interrupt pin inta_l, is used reset to 01h 6.3.30 bridge control register ? offset 3ch bit function type description 16 parity error response enable rw 0: ignore parity errors on the secondary 1: enable parity erro r detection on secondary forward bridge ? controls the response to uncorrectable a ddress attribute and data errors on the secondary reverse bridge ? controls the setting of the master data parity error bit in response to a received poisoned tlp from the secondary (pcie link) reset to 0 17 serr_l enable rw 0: disable the forwarding of serr_l to err_fatal and err_nonfatal 1: enable the forwarding of serr_l to err_fatal and err_nonfatal reset to 0 (forward bridge) ro bit for reverse bridge 18 isa enable rw 0: forward downstream all i/o addresses in the address range defined by the i/o base and limit registers 1: forward upstream all i/o addresses in the address range defined by the i/o base and limit registers that are in the first 64kb of pci i/o address space (top 768 bytes of each 1kb block) reset to 0 19 vga enable rw 0: do not forward vga compatible memory and i/o addresses from the primary to secondary, unless they are enabled for forwarding by the defined i/o and memory address ranges 1: forward vga compatible memory and i/o addresses from the primary and secondary (if the i/o enable and memory enable bits are set), independent of the isa enable bit 20 vga 16-bit decode rw 0: execute 10- bit address decodes on vga i/o accesses 1: execute 16-bit address decode on vga i/o accesses reset to 0 21 master abort mode rw 0: do not report mast er aborts (return ffffffffh on reads and discards data on write) 1: report master abort by signaling target abort if possible or by the assertion of serr_l (if enabled). reset to 0 22 secondary interface reset rw 0: do not force the assertion of reset_l on secondary pci bus for forward bridge, or do not generate a hot rese t on the pcie link for reverse bridge 1: force the assertion of reset_l on secondary pci bus for forward bridge, or generate a hot reset on the pcie link for reverse bridge reset to 0 23 fast back-to-back enable ro fast back-to-back not supported reset to 0
pi7c9x111sl pcie-to-pci reversible bridge page 34 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 bit function type description 24 primary master timeout rw 0: primary discard timer counts 2 15 pci clock cycles 1: primary discard timer counts 2 10 pci clock cycles forward bridge ? bit is ro and ignored by the pi7c9x111sl reset to 0 25 secondary master timeout rw 0: secondary discard timer counts 2 15 pci clock cycles 1: secondary discard timer counts 2 10 pci clock cycles reverse bridge ? bit is ro and ignored by pi7c9x111sl reset to 0 26 master timeout status rwc bit is set when the discard timer expires and a delayed completion is discarded at the pci interface for the forward or reverse bridge reset to 0 27 discard timer serr_l enable rw bit is set to enable to gene rate err_nonfatal or err_fatal for forward bridge, or assert p_serr_l for reverse bridge as a result of the expiration of the discard timer on the pci interface. reset to 0 31:28 reserved ro reset to 0000 6.3.31 pci data buffering co ntrol register ? offset 40h bit function type description 0 secondary internal arbiter?s park function rw 0: park to the last master 1: park to pi7c9x111sl secondary port reset to 0 1 memory read prefetching dynamic control disable rw 0: enable memory read prefetchi ng dynamic control for pci to pcie read 1: disable memory read prefetching dynamic control for pci to pcie read reset to 0 2 completion data prediction control rw 0: enable completion data pr ediction for pci to pcie read. 1: disable completion data prediction reset to 0 3 cfg type0-to-type1 conversion enable rw 0: cfg type0-to-type1 conversion is disabled. 1: cfg type0-to-type1 conversion is enabled if the ad[31:28] is all 1s. bridge will ignore the ad[0] and always treats the cfg transaction as type 1, other ad bit (except ad[31:28], ad[0]) must meet the type 1 format reset to 0 5:4 pci read multiple prefetch mode rw 00: one cache line prefetch if me mory read multiple address is in prefetchable range at the pci interface 01: full prefetch if address is in pref etchable range at pci interface, and the pi7c9x111sl will keep remaining data after it disconnects the external master during burst read with read multiple command until the discard timer expires 10: full prefetch if address is in prefetchable range at pci interface 11: full prefetch if address is in pr efetchable range at pci interface and the pi7c9x111sl will keep remaining data af ter the read multiple is terminated either by an external master or by the pi7c9x111sl, until the discard time expires reset to 10
pi7c9x111sl pcie-to-pci reversible bridge page 35 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 bit function type description 7:6 pci read line prefetch mode rw 00: once cache line prefetch if memory read address is in prefetchable range at pci interface 01: full prefetch if address is in pr efetchable range at pci interface and the pi7c9x111sl will keep remaining data after it is disconnected by an external master during burst read with read line command, until discard timer expires 10: full prefetch if memory read line a ddress is in prefetchable range at pci interface 11: full prefetch if address is in pr efetchable range at pci interface and the pi7c9x111sl will keep remaining data af ter the read line is terminated either by an external master or by the pi7c9x111sl, until the discard timer expires reset to 00 9:8 pci read prefetch mode rw 00: one cache line prefet ch if memory read address is in prefetchable range at pci interface 01: reserved 10: full prefetch if memory read addr ess is in prefetchable range at pci interface 11: disconnect on the first dword reset to 00 10 pci special delayed read mode enable rw 0: retry any master at pci bus that repeats its transaction with command code changes. 1: allows any master at pci bus to change memory command code (mr, mrl, mrm) after it has received a re try. the pi7c9x111sl will complete the memory read transaction and return da ta back to the mast er if the address and byte enables are the same. reset to 0 11 optional malformed packet checking enable rw 0: optional malformed p acket checking is disabled 1: optional malformed packet checking is enabled reset to 0 14:12 maximum memory read byte count rw maximum byte count is used by the pi7c9x111sl when generating memory read requests on the pcie link in response to a memory read initiated on the pci bus and bit [9:8], bit [7:6], and bit [5:4] are set to ?full prefetch?. 000: 512 bytes (default) 001: 128 bytes 010: 256 bytes 011: 512 bytes 100: 1024 bytes 101: 2048 bytes 110: 4096 bytes 111: 512 bytes reset to 000 6.3.32 chip control 0 register ? offset 40h bit function type description 15 flow control update control rw 0: flow control is updated for every two credits available 1: flow control is updated for every on credit available reset to 0
pi7c9x111sl pcie-to-pci reversible bridge page 36 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 bit function type description 16 pci retry counter status rwc 0: the pci retr y counter has not expired since the last reset 1: the pci retry counter has expired since the last reset reset to 0 18:17 pci retry counter control rw 00: no expiration limit 01: allow 256 retries before expiration 10: allow 64k retries before expiration 11: allow 2g retrie s before expiration reset to 00 19 pci discard timer disable rw 0: enable the pci di scard timer in conjunction with bit [27] offset 3ch (bridge control register) 1: disable the pci discard timer in conjunction with bit [27] offset 3ch (bridge control register) reset to 0 20 pci discard timer short duration rw 0: use bit [24] offset 3ch for forward bridge or bit [25] offset 3ch for reverse bridge to indicate how many pci clocks should be allowed before the pci discard timer expires 1: 64 pci clocks allowed before the pci discard timer expires reset to 0 22:21 configuration request retry timer counter value control rw 00: timer expires at 25us 01: timer expires at 0.5ms 10: timer expires at 5ms 11: timer expires at 25ms reset to 01 23 delayed transaction order control rw 0: enable out-of-order capability between delayed transactions 1: disable out-of-order capability between delayed transactions reset to 0 25:24 completion timer counter value control rw 00: timer expires at 50us 01: timer expires at 10ms 10: timer expires at 50ms 11: timer disabled reset to 01 26 isochronous traffic support enable rw 0: all memory transactions from pci to pcie will be mapped to tc0 1: all memory transactions from pci to pcie will be mapped to traffic class defined in bit [29:27] of offset 40h. reset to 0 29:27 traffic class used for isochronous traffic rw reset to 001 30 power saving mode enable rw =0 : disable the power saving mode; =1 : enable the power saving mode, and the internal clock for mac/dll/tlp and pci logic is disabled at l1s and l1 state. 31 primary configuration access lockout rw =0 : 9x111 configura tion space can be accessed from both interface. =1 : 9x111 configuration space can only be accessed from the secondary interface. primary bus accessed receives completion with crs status for forward bridge, or target retry for reverse bridge.
pi7c9x111sl pcie-to-pci reversible bridge page 37 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 6.3.33 reserved register ? offset 44h bit function type description 31:0 reserved ro reset to 00000000h 6.3.34 arbiter enable register ? offset 48h bit function type description 0 enable arbiter 0 rw 0: disable arb itration for internal pi7c9x111sl request 1: enable arbitration for internal pi7c9x111sl request reset to 1 1 enable arbiter 1 rw 0: disable arbitration for master 1 1: enable arbitration for master 1 reset to 1 2 enable arbiter 2 rw 0: disable arbitration for master 2 1: enable arbitration for master 2 reset to 1 3 enable arbiter 3 rw 0: disable arbitration for master 3 1: enable arbitration for master 3 reset to 1 4 reserved rw reset to 1 5 reserved ro reset to 0 6 reserved ro reset to 0 7 reserved ro reset to 0 8 reserved ro reset to 0 6.3.35 arbiter mode register ? offset 48h bit function type description 9 external arbiter bit rw =0 : enable internal arbiter =1: when using an external arbiter reset to 0 10 broken master timeout enable rw 0: broken master timeout disable 1: this bit enables the internal arb iter to count 16 pci bus cycles while waiting for frame_l to become activ e when a device?s pci bus gnt is active and the pci bus is idle. if the broken master timeout expires, the pci bus gnt for the device is de-asserted. reset to 0 11 broken master refresh enable rw 0: a broken master will be ignored forever after de-asserting its req_l for at least 1 clock 1: refresh broken master state after a ll the other masters have been served once reset to 0 19:12 arbiter fairness counter rw 08h: these bits are the initialization value of a count er used by the internal arbiter. it controls the number of pc i bus cycles that the arbiter holds a device?s pci bus gnt active after detecting a pci bus req_l from another device. the counter is reloaded whenever a new pci bus gnt is asserted. for every new pci bus gnt, the counter is armed to decrement when it detects the new fall of frame_l. if the arbiter fairness counter is set to 00h, the arbiter will not remove a device?s pci bus gnt until the device has de- asserted its pci bus req. reset to 08h
pi7c9x111sl pcie-to-pci reversible bridge page 38 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 bit function type description 20 gnt_l output toggling enable rw 0: gnt_l not de-asserted afte r granted master assert frame_l 1: gnt_l de-asserts for 1 clock after 2 cl ocks of the granted master asserting frame_l reset to 0 21 reserved ro reset to 0 6.3.36 arbiter priority register ? offset 48h bit function type description 22 arbiter priority 0 rw 0: low prio rity request to internal pi7c9x111sl 1: high priority request to internal pi7c9x111sl reset to 1 23 arbiter priority 1 rw 0: low priority request to master 1 1: high priority request to master 1 reset to 0 24 arbiter priority 2 rw 0: low priority request to master 2 1: high priority request to master 2 reset to 0 25 arbiter priority 3 rw 0: low priority request to master 3 1: high priority request to master 3 reset to 0 26 arbiter priority 4 rw 0: low priority request to master 4 1: high priority request to master 4 reset to 0 27 reserved ro reset to 0 28 reserved ro reset to 0 29 reserved ro reset to 0 30 reserved ro reset to 0 31 reserved ro reset to 0 6.3.37 reserved registers ? offset 4ch 6.3.38 memory readsmart base lowe r 32-bit register 1 ? offset 50h bit function type description 31:0 memory readsmart base lower 32-bit register 1 rw memory readsmart base address 1 in conjunction with memory readsmart base lower 32-bit register 1 and memo ry readsmart range size register 1, defines address range 1 in which pci memory read are allowed (or not allowed) to use the readsmart mode which is controlled by bit [7:4] of 40h. reset to 00000000h 6.3.39 memory readsmart base uppe r 32-bit register 1 ? offset 54h bit function type description 31:0 memory readsmart base upper 32-bit register 1 rw bit[63:32] of memory readsmart base address 1 reset to 00000000h
pi7c9x111sl pcie-to-pci reversible bridge page 39 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 6.3.40 memory readsmart range control register 1 ? offset 58h bit function type description 31:1 memory readsmart range address 1 rw define the size of the range 1, maxi mum 4g byte with granuity of 2 bytes 0 memory readsmart range control rw memory readsmart range control register 0: any pci memory read with address falling in the range are not allowed to use readsmart mode. 1: only pci memory read with address falling in the range are allowed to use readsmart mode. reset to 0 6.3.41 memory readsmart base lowe r 32-bit register 2 ? offset 5ch bit function type description 31:0 readsmart memory base lower 32-bit register 2 rw memory readsmart base address 1 in conjunction with memory readsmart base lower 32-bit register 2 and memo ry readsmart range size register 2, defines address range 1 in which pci memory read are allowed (or not allowed) to use the readsmart mode which is controlled by bit [7:4] of 40h. reset to 00000000h 6.3.42 memory readsmart base uppe r 32-bit register 2 ? offset 60h bit function type description 31:0 memory readsmart base upper 32-bit register 2 rw bit[63:32] of memory readsmart base address 2 reset to 00000000h 6.3.43 memory readsmart range size register 2 ? offset 64h bit function type description 31:0 memory readsmart range size register 2 rw memory readsmart range address 2 defines the size of the range 2, maximum 4g byte reset to 00000000h 6.3.44 express transmitter/receiver register ? offset 68h bit function type description
pi7c9x111sl pcie-to-pci reversible bridge page 40 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 bit function type description 1:0 nominal driver current control rw 00: 20ma 01: 10ma 10: 28ma 11: reserved reset to 00 5:2 driver current scale multiple control rw 0000: 1.00 x nominal driver current 0001: 1.05 x nominal driver current 0010: 1.10 x nominal driver current 0011: 1.15 x nominal driver current 0100: 1.20 x nominal driver current 0101: 1.25 x nominal driver current 0110: 1.30 x nominal driver current 0111: 1.35 x nominal driver current 1000: 0.60 x nominal driver current 1001: 0.65 x nominal driver current 1010: 0.70 x nominal driver current 1011: 0.75 x nominal driver current 1100: 0.80 x nominal driver current 1101: 0.85 x nominal driver current 1110: 0.90 x nominal driver current 1111: 0.95 x nominal driver current reset to 0000 7:6 receiver equalization control for 0.13um phy rw =00 : max rx equalization, for input jitter > 0.25 ui =01 : min rx equaliza tion, for input jitter be tween 0.1 ui and 0.25 ui =1x : rx equalization off 11:8 driver de-emphasis level control rw 0000: 0.00 db 0001: -0.35 db 0010: -0.72 db 0011: -1.11 db 0100: -1.51 db 0101: -1.94 db 0110: -2.38 db 0111: -2.85 db 1000: -3.35 db 1001: -3.88 db 1010: -4.44 db 1011: -5.04 db 1100: -5.68 db 1101: -6.38 db 1110: -7.13 db 1111: -7.96 db reset to 1000 13:12 transmitter termination control rw 00: 52 ohms 01: 57 ohms 10: 43 ohms 11: 46 ohms reset to 00 15:14 receiver termination control rw 00: 52 ohms 01: 57 ohms 10: 43 ohms 11: 46 ohms reset to 00 29:16 reserved ro reset to 00h 6.3.45 upstream memory write fragment control register ? offset 68h bit function type description
pi7c9x111sl pcie-to-pci reversible bridge page 41 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 bit function type description 31:30 memory write fragment control rw upstream memory write fragment control 00: fragment at 32-byte boundary 01: fragment at 64-byte boundary 1x: fragement at 128-byte boundary reset to 10h 6.3.46 reserved register ? offset 6ch 6.3.47 eeprom autoload control/status register ? offset 70h bit function type description 0 initiate eeprom read or write cycle rw this bit will be reset to 0 afte r the eeprom operation is finished. 0: eeprom autoload disabled 0 -> 1: starts the eeprom read or write cycle reset to 0 1 control command for eeprom rw 0: read 1: write reset to 0 2 eeprom error ro 0: eeprom acknowledge is always received during the eeprom cycle 1: eeprom acknowledge is not received during eeprom cycle reset to 0 3 eprom autoload complete status ro 0: eeprom autoload is not successfully completed 1: eeprom autoload is successfully completed reset to 0 5:4 eeprom clock frequency control rw where pclk is 125mhz 00: pclk / 4096 01: pclk / 2048 10: pclk / 1024 11: pclk / 128 reset to 00 6 eeprom autoload control rw 0: enable eeprom autoload 1: disable eeprom autoload reset to 0 7 fast eeprom autoload control rw =0: normal speed of eeprom autoload =1: speeds up eeprom autoload by 8 times reset to 1 8 eeprom autoload status ro 0: eeprom autoload is not on going 1: eeprom autoload is on going reset to 0 15:9 eeprom word address rw eeprom word address for eeprom cycle reset to 0000000 31:16 eeprom data rw eeprom data to be written into the eeprom reset to 0000h
pi7c9x111sl pcie-to-pci reversible bridge page 42 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 6.3.48 reserved register ? offset 74h 6.3.49 gpio data and control register ? offset 78h bit function type description 11:0 reserved ro reset to 000h 15:12 gpio output write-1-to- clear rw reset to 0h 19:16 gpio output write-1-to-set rw reset to 0h 23:20 gpio output enable write- 1-to-clear rw reset to 0h 27:24 gpio output enable write- 1-to-set rw reset to 0h 31:28 gpio input data register ro reset to 0h 6.3.50 reserved register ? offset 7ch 6.3.51 pci-x capability id register ? offset 80h bit function type description 7:0 pci-x capability id ro pci-x capability id reset to 07h 6.3.52 next capability pointer register ? offset 80h bit function type description 15:8 next capability pointer ro point to power management reset to 90h 6.3.53 pci-x secondary status register ? offset 80h bit function type description 16 64-bit device on secondary bus interface ro 64-bit not supported reset to 0 17 133mhz capable ro 133mhz capable on seconda ry interface. this bit is always ro. 18 split completion discarded ro split completion discarded this bit is always ro. reset to 0 19 unexpected split completion rwc =0: no unexpect ed split completion has been recevied. =1: an unexpected sp lit completion has been recevied with the requeste id equaled to th e bridge's secondary port number, device number 00h, and function number 0 on the bridge secondary interface. this bit is ro for forward bridge. reset to 0 20 split completion overrun ro this bit is always ro. reset to 0 21 split request delayed rwc/ro =0: the br idge has not delayed a split request. =1: the bridge has delayed a split reque st because the bridge cannot forward a transaction to secondary port due to not enough room within the limit specified in the split transaction co mmitment limit field in the downstream split transaction control register. th is bit is ro for forward bridge. reset to 0
pi7c9x111sl pcie-to-pci reversible bridge page 43 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 bit function type description 24:22 secondary clock fre quency ro these bits are only meaningful in forward bridge mode. in reverse bridge mode, all three bits are set to zero. 000: conventional pci mode (minim um clock period not applicable) 001: 66mhz (minimum clock period is 15ns) 010: 100 to 133mhz (minimum clock period is 7.5ns) 011: reserved 1xx: reserved reset to 000 31:25 reserved ro 0000000 6.3.54 pci-x bridge status register ? offset 84h bit function type description 2:0 function number ro function number; the functi on number (ad[10:8] of a type-0 configuration transaction) to which the bridge responds. reset to 000 7:3 device number ro device number; the device number (ad[15:11] of a type-0 configuration transaction) is assigned to the bridge by the connection of system hardware. each time the bridge is addressed by a configuration write transaction, the bridge updates this register with the contents of ad[15:11] of the address phase of the configuration transaction, regardless of which register in the bridge is addressed by the transacti on. the bridge is addressed by a configuration write tran saction if all of the following are true: ? the transaction uses a configuration write command. ? idsel is asserted during the address phase. ? ad[1:0] are 00 (type-0 configuration transaction). ? ad[10:8] of the configuration addre ss contain the appropriate function number. reset to 11111 15:8 bus number ro bus number; it is an add itional address from which the contents of the primary bus number register on type-1 configuration space header is read. the bridge uses the bus number, device number, and function number fields to create the completer id when res ponding with a split completion to a read of an internal bridge register. these fields are also used for cases when one interface is in conventional pci mode and the other is in pcix mode. reset to 11111111 16 64-bit device on primary bus interface ro 64-bit device. reset to 0 17 133mhz capable ro 133mhz capable on prim ary interface. this bit is always ro. reset to 0 in forward bridge mode or 1 in reverse bridge mode 18 split completion discarded ro this bit is always ro. reset to 0 19 unexpected split completion rwc =0: no unexpected split co mpletion has been recevied. =1: an unexpected split completion has b een recevied with the request id equaled to the bridge's primary port number, device number, and function number on the bridge primary interface. this bit is ro for reverse bridge. reset to 0 20 split completion overrun ro this bit is always ro. reset to 0 21 split request delayed rwc when this bit is set to 1, a split request is delayed because pi7c9x111sl is not able to forward the split request tr ansaction to its primary bus due to insufficient room with in the limit specified in the split transaction commitment limit field of the downstream split transaction control register reset to 0 31:22 reserved ro 0000000000 6.3.55 upstream split transaction register ? offset 88h
pi7c9x111sl pcie-to-pci reversible bridge page 44 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 bit function type description 15:0 upstream split transaction capability ro upstream split transaction capability sp ecifies the size of the buffer (in the unit of adqs) to store split completions fo r memory read. it applies to the requesters on the secondary bus in addressing the completers on the primary bus. the 0010h value shows that the buffer has 16 adqs or 2k bytes storage reset to 0010h 31:16 upstream split transaction commitment limit rw upstream split transaction commitment limit indicates the cumulative sequence size of the commitment limit in units of adqs. this field can be programmed to any value or equal to th e content of the split capability field. for example, if the limit is set to ffffh, pi7c9x111sl is allowed to forward all split requests of any size re gardless of the amount of buffer space available. the split transaction commitment limit is set to 0010h that is the same value as the split transaction capability. reset to 0010h 6.3.56 downstream split transaction register ? offset 8ch bit function type description 15:0 downstream split transaction capability ro downstream split transaction capability specifies the size of the buffer (in the unit of adqs) to store split completions for memory read. it applies to the requesters on the primary bus in addressing the completers on the secondary bus. the 0010h value shows that the buffer has 16 adqs or 2k bytes storage reset to 0010h 31:16 downstream split transaction commitment limit rw downstream split transaction comm itment limit indicates the cumulative sequence size of the commitment limit in units of adqs. this field can be programmed to any value or equal to th e content of the split capability field. for example, if the limit is set to ffffh, pi7c9x111sl is allowed to forward all split requests of any size re gardless of the amount of buffer space available. the split transaction commitment limit is set to 0010h that is the same value as the split transaction capability. reset to 0010h 6.3.57 power management id register ? offset 90h bit function type description 7:0 power management id ro po wer management id register reset to 01h 6.3.58 next capability pointer register ? offset 90h bit function type description 15:8 next pointer ro next pointer (point to subsystem id and subsystem vendor id) reset to a8h 6.3.59 power management capability register ? offset 90h bit function type description 18:16 version number ro version number that complies with revision 2.0 of the pci power management interface specification. reset to 010
pi7c9x111sl pcie-to-pci reversible bridge page 45 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 bit function type description 19 pme clock ro pme clock is not required for pme_l generation reset to 0 20 reserved ro reset to 0 21 device specific initialization (dsi) ro dsi ? no special initialization of th is function beyond the standard pci configuration header is required following transition to the d0 un-initialized state reset to 0 24:22 aux current ro 000: 0ma 001: 55ma 010: 100ma 011: 160ma 100: 220ma 101: 270ma 110: 320ma 111: 375ma reset to 001 25 d1 power management ro d1 pow er management is not supported reset to 0 26 d2 power management ro d2 pow er management is not supported reset to 0 31:27 pme_l support ro pme_l is supported in d3 cold, d3 hot, and d0 states. reset to 11001 6.3.60 power management control and status register ? offset 94h bit function type description 1:0 power state rw power state is used to determine the current power state of pi7c9x111sl. if a non-implemented state is written to this register, pi7c9x111sl will ignore the write data. when present st ate is d3 and changing to d0 state by programming this register, the power state change causes a device reset without activating the rese t_l of pci bus interface 00: d0 state 01: d1 state not implemented 10: d2 state not implemented 11: d3 state reset to 00 7:2 reserved ro reset to 000000 8 pme enable rws 0: pme_l assertion is disabled 1: pme_l assertion is enabled reset to 0 12:9 data select ro data re gister is not implemented reset to 0000 14:13 data scale ro data re gister is not implemented reset to 00 15 pme status rwcs pme_l is supported reset to 0 6.3.61 pci-to-pci support exten sion register ? offset 94h bit function type description
pi7c9x111sl pcie-to-pci reversible bridge page 46 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 bit function type description 21:16 reserved ro reset to 000000 22 b2/b3 support ro 0: b2 / b3 not support for d3hot reset to 0 23 pci bus power/clock control enable ro 0: pci bus power/clock disabled reset to 0 31:24 data register ro data register is not implemented reset to 00h 6.3.62 reserved registers ? offset 98h ? 9ch 6.3.63 capability id register ? offset a0h bit function type description 7:0 capability id ro capability id fo r slot identification. si is o ff by default but can be turned on through eeprom interface reset to 04h 6.3.64 next pointer register ? offset a0h bit function type description 15:8 next pointer ro next pointer ? poi nts to pci express capabilities register reset to b0h 6.3.65 slot number register ? offset a0h bit function type description 20:16 expansion slot number rw expansion slot number reset to 00000 21 first in chassis rw first in chassis reset to 0 23:22 reserved ro reset to 00 6.3.66 chassis number register ? offset a0h bit function type description 31:24 chassis number rw chassis number reset to 00h 6.3.67 secondary clock and clkrun control register ? offset a4h bit function type description 1:0 s_clkout0 enable rw s_clkout (slot 0) enable for forward bridge mode only 00: enable s_clkout0 01: enable s_clkout0 10: enable s_clkout0 11: disable s_clkout0 and driven low reset to 00
pi7c9x111sl pcie-to-pci reversible bridge page 47 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 bit function type description 3:2 s_clkout1 enable rw s_clkout (slot 1) enable for forward bridge mode only 00: enable s_clkout1 01: enable s_clkout1 10: enable s_clkout1 11: disable s_clkout1 and driven low reset to 00 5:4 s_clkout2 enable rw s_clkout (slot 2) enable for forward bridge mode only 00: enable s_clkout2 01: enable s_clkout2 10: enable s_clkout2 11: disable s_clkout2 and driven low reset to 00 7:6 s_clkout3 enable rw s_clkout (slot 3) enable for forward bridge mode only 00: enable s_clkout3 01: enable s_clkout3 10: enable s_clkout3 11: disable s_clkout3 and driven low reset to 00 8 reserved ro reset to 0h 9 reserved ro reset to 0h 10 reserved ro reset to 0h 11 reserved ro reset to 0h 12 reserved ro reset to 0h 13 secondary clock stop status ro secondary clock stop status 0: secondary clock not stopped 1: secondary clock stopped reset to 0 14 secondary clkrun protocol enable rw 0: disable protocol 1: enable protocol reset to 0 15 clkrun mode rw 0: stop the secondary cl ock only when bridge is at d3hot state 1: stop the secondary clock whenever the secondary bus is idle and there are no requests from the primary bus reset to 0 16 aspm l0s enable control rw 0: bridge may ente r aspm l0s regardless if receiver is electrical idle 1: bridge may enter aspm l0s only if receiver is electrical idle reset to 1 18:17 scrambling control rw reset to 0 31:19 reserved ro reset to 0 6.3.68 capability id register ? offset a8h bit function type description 7:0 capability id ro capability id for subsystem id and subsystem vendor id reset to 0dh 6.3.69 next pointer register ? offset a8h bit function type description
pi7c9x111sl pcie-to-pci reversible bridge page 48 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 bit function type description 15:8 next item pointer ro next item pointer (point to pci express capability by default but can be programmed to a0h if slot identif ication capability is enabled) reset to b0h 6.3.70 reserved register ? offset a8h bit function type description 31:16 reserved ro reset to 0000h 6.3.71 subsystem vendor id register ? offset ach bit function type description 15:0 subsystem vendor id ro subsystem vendor id id entifies the particular add-in card or subsystem reset to 00h 6.3.72 subsystem id register ? offset ach bit function type description 31:16 subsystem id ro subsystem id identifie s the particular add-in card or subsystem reset to 00h 6.3.73 pci express capability id register ? offset b0h bit function type description 7:0 pci express capability id ro pci express capability id reset to 10h 6.3.74 next capability pointer register ? offset b0h bit function type description 15:8 next item pointer ro next capabilities pointer register reset to f0h 6.3.75 pci express capabilit y register ? offset b0h bit function type description 19:16 capability version ro reset to 1h 23:20 device / port type ro 0000: pci express endpoint device 0001: legacy pci express endpoint device 0100: root port of pci express root complex 0101: upstream port of pci express switch 0110: downstream port of pci express switch 0111: pci express to pci bridge 1000: pci to pci express bridge others: reserved reset to 7h for forward bridge or 8h for reverse bridge 24 slot implemented ro reset to 0 for fo rward bridge or 1 for reverse bridge 29:25 interrupt message nu mber ro reset to 0h 31:30 reserved ro reset to 0 6.3.76 device capability register ? offset b4h
pi7c9x111sl pcie-to-pci reversible bridge page 49 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 bit function type description 2:0 maximum payload size ro 000: 128 bytes 001: 256 bytes 010: 512 bytes 011: 1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved reset to 2h 4:3 phantom functions ro no phantom functions supported reset to 00 5 8-bit tag field ro 8-bit tag field supported reset to 1 8:6 endpoint l0?s latency ro endpoint l0?s acceptable latency 000: less than 64 ns 001: 64 ? 128 ns 010: 128 ? 256 ns 011: 256 ? 512 ns 100: 512 ns ? 1 us 101: 1 ? 2 us 110: 2 ? 4 us 111: more than 4 us reset to 000 11:9 endpoint l1?s latency ro endpoint l1?s acceptable latency 000: less than 1 us 001: 1 ? 2 us 010: 2 ? 4 us 011: 4 ? 8 us 100: 8 ? 16 us 101: 16 ? 32 us 110: 32 ? 64 us 111: more than 64 us reset to 000 12 attention button present ro 0: if hot plug is disabled 1: if hot plug is enabled at forward bridge reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 13 attention indicator present ro 0: if hot plug is disabled 1: if hot plug is enable at forward bridge reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 14 power indicator present ro 0: if hot plug is disabled 1: if hot plug is enable at forward bridge reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 17:15 reserved ro reset to 000 25:18 captured slot power limit value ro these bits are set by the set_slot_power_limit message reset to 00h 27:26 captured slot power limit scale ro this value is set by the set_slot_power_limit message reset to 00 31:28 reserved ro reset to 0h
pi7c9x111sl pcie-to-pci reversible bridge page 50 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 6.3.77 device control register ? offset b8h bit function type description 0 correctable error reporting enable rw reset to 0h 1 non-fatal error reporting enable rw reset to 0h 2 fatal error reporting enable rw reset to 0h 3 unsupported request reporting enable rw reset to 0h 4 relaxed ordering enable ro relaxed ordering disabled reset to 0h 7:5 max payload size rw this field sets th e maximum tlp payload size for the pi7c9x111sl 000: 128 bytes 001: 256 bytes 010: 512 bytes 011:1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved reset to 000 8 extended tag field enable rw reset to 0 9 phantom functions enable ro phantom functions not supported reset to 0 10 auxiliary power pm enable ro auxiliary power pm not supported reset to 0 11 no snoop enable ro bridge never sets the no snoop attribute in the transaction it initiates reset to 0 14:12 maximum read request size rw this field sets the maximum read request size for the device as a requester 000: 128 bytes 001: 256 bytes 010: 512 bytes 011: 1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved reset to 2h 15 configuration retry enable rw reset to 0 6.3.78 device status register ? offset b8h bit function type description 16 correctable error detected rwc reset to 0 17 non-fatal error detected rwc reset to 0 18 fatal error detected rwc reset to 0 19 unsupported request detected rwc reset to 0 20 aux power detected ro reset to 1 21 transaction pending ro 0: no transaction is pending on transaction layer interface 1: transaction is pending on transaction layer interface reset to 0 31:22 reserved ro reset to 0000000000
pi7c9x111sl pcie-to-pci reversible bridge page 51 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 6.3.79 link capability register ? offset bch bit function type description 3:0 maximum link speed ro indicates th e maximum speed of the express link 0001: 2.5gb/s link reset to 1 9:4 maximum link width ro indicates the maximu m width of the express link (x1 at reset) 000000: reserved 000001: x1 000010: x2 000100: x4 001000: x8 001100: x12 010000: x16 100000: x32 reset to 000001 11:10 aspm support ro this field indicates the level of active state power management support 00: reserved 01: l0?s entry supported 10: reserved 11: l0?s and l1?s supported reset to 11 14:12 l0?s exit latency ro reset to 3h 17:15 l1?s exit latency ro reset to 0/6h 23:18 reserved ro reset to 0/1h 31:24 port number ro reset to 00h 6.3.80 link control register ? offset c0h bit function type description 1:0 aspm control rw this field controls th e level of aspm supported on the express link 00: disabled 01: l0?s entry enabled 10: l1?s entry enabled 11: l0?s and l1?s entry enabled reset to 00 2 reserved ro reset to 0 3 read completion boundary (rcb) ro read completion boundary not supported reset to 0 4 link disable ro / rw ro for forward bridge reset to 0 5 retrain link ro / rw ro for forward bridge reset to 0 6 common clock configuration rw reset to 0 7 extended sync rw reset to 0 15:8 reserved ro reset to 00h 6.3.81 link status register ? offset c0h bit function type description
pi7c9x111sl pcie-to-pci reversible bridge page 52 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 bit function type description 19:16 link speed ro this field indicates the negotiated speed of the express link 001: 2.5gb/s link reset to 1h 25:20 negotiated link width ro 000000: reserved 000001: x1 000010: x2 000100: x4 001000: x8 001100: x12 010000: x16 100000: x32 reset to 000001 26 link train error ro reset to 0 27 link training ro reset to 0 28 slot clock configuration ro reset to 1 31:29 reserved ro reset to 0 6.3.82 slot capability register ? offset c4h bit function type description 0 attention button present ro 0: if hot plug is disabled 1: if hot plug is enabled at reverse bridge reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 1 power controller present ro reset to 0 2 mrl sensor present ro 0: if hot plug is disabled 1: if hot plug is enabled at reverse bridge reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 3 attention indicator present ro 0: if hot plug is disabled 1: if hot plug is enabled at reverse bridge reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 4 power indicator present ro 0: if hot plug is disabled 1: if hot plug is enabled at reverse bridge reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 5 hot plug surprise ro reset to 0 6 hot plug capable ro 0: if hot plug is disabled 1: if hot plug is enabled at reverse bridge reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 14:7 slot power limit value ro reset to 00h 16:15 slot power limit scale ro reset to 00 18:17 reserved ro reset to 00 31:19 physical slot number ro reset to 0 6.3.83 slot control register ? offset c8h bit function type description 0 attention button present enable rw reset to 0 1 power fault detected enable rw reset to 0
pi7c9x111sl pcie-to-pci reversible bridge page 53 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 bit function type description 2 mrl sensor changed enable rw reset to 0 3 presence detect changed enable rw reset to 0 4 command completed interrupt enable rw reset to 0 5 hot plug interrupt enable rw reset to 0 7:6 attention indicator control rw reset to 0 9:8 power indicator control rw reset to 0 10 power controller control rw reset to 0 15:11 reserved ro reset to 0 6.3.84 slot status register ? offset c8h bit function type description 16 attention button pressed ro reset to 0 17 power fault detected ro reset to 0 18 mrl sensor changed ro reset to 0 19 presence detect changed ro reset to 0 20 command completed ro reset to 0 21 mrl sensor state ro reset to 0 22 presence detect state ro reset to 0 31:23 reserved ro reset to 0 6.3.85 xpip configuration register 0 ? offset cch bit function type description 0 hot reset enable rw reset to 0 1 loopback function enable rw reset to 0 2 cross link function enable rw reset to 0 3 software direct to configuration state when in ltssm state rw reset to 0 4 internal selection for debug mode rw reset to 0 7:5 negotiate lane number of times rw reset to 3h 12:8 ts1 number counter rw reset to 10h 15:13 reserved ro reset to 0 31:16 ltssm enter l1 timer default value rw reset to 0400h 6.3.86 xpip configuration register 1 ? offset d0h bit function type description 9:0 l0?s lifetime timer rw reset to 0 15:10 reserved ro reset to 0 31:16 l1 lifetime timer rw reset to 0 6.3.87 xpip configuration register 2 ? offset d4h bit function type description 7:0 cdr recovery time (in the number of fts order sets) rw reset to 54h a fast training sequence order set co mposes of one k28.5 (com) symbol and three k28.1 symbols. 14:8 l0?s exit to l0 latency rw reset to 2h 15 reserved ro reset to 0 22:16 l1 exit to l0 latency rw reset to 19h 23 reserved ro reset to 0
pi7c9x111sl pcie-to-pci reversible bridge page 54 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5
pi7c9x111sl pcie-to-pci reversible bridge page 55 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 6.3.88 l0 enter l1 waiting period counter ? offset d4h bit function type description 31:24 l0 enter l1 waiting period counter rw l0 enter l1 waiting period counter =d0: 128ms =d1: 129ms . . =d127: 256ms =d128: 0ms =d129: 1ms . . =d255: 127ms reset to 00h 6.3.89 capability id register ? offset d8h bit function type description 7:0 capability id for vpd register ro reset to 03h 6.3.90 next pointer register ? offset d8h bit function type description 15:8 next pointer ro next pointer (f0h, points to msi capabilities) reset to f0h 6.3.91 vpd register ? offset d8h bit function type description 17:16 reserved ro reset to 0 23:18 vpd address for read/write cycle rw reset to 0 30:24 reserved ro reset to 0 31 vpd operation rw 0: generate a read cycle fr om the eeprom at the vpd address specified in bits [7:2] of offset d8h. this b it remains at ?0? until eeprom cycle is finished, after which the bit is then set to ?1?. data for reads is available at register ech. 1: generate a write cycle to the eep rom at the vpd address specified in bits [7:2] of offset d8h. this b it remains at ?1? until eeprom cycle is finished, after which it is then cleared to ?0?. reset to 0 6.3.92 vpd data register ? offset dch bit function type description 31:0 vpd data rw vpd data (eeprom data [address + 0x40]) the least significant byte of this regist er corresponds to the byte of vpd at the address specified by the vpd addre ss register. the data read form or written to this register uses the normal pci byte tr ansfer capabilities. reset to 0
pi7c9x111sl pcie-to-pci reversible bridge page 56 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 6.3.93 reserved registers ? offset e0h ? ech 6.3.94 message signaled interrupts id register ? f0h bit function type description 7:0 capability id for msi registers ro reset to 05h 6.3.95 next capabilities pointer register ? f0h bit function type description 15:8 next pointer ro next pointer (00h indicates the end of capabilities) reset to 00h 6.3.96 message control register ? offset f0h bit function type description 16 msi enable rw 0: disable msi and default to intx for interrupt 1: enable msi for interrupt service and ignore intx interrupt pins 19:17 multiple message capable ro 000: 1 message requested 001: 2 messages requested 010: 4 messages requested 011: 8 messages requested 100: 16 messages requested 101: 32 messages requested 110: reserved 111: reserved reset to 000 22:20 multiple message enable rw 000: 1 message requested 001: 2 messages requested 010: 4 messages requested 011: 8 messages requested 100: 16 messages requested 101: 32 messages requested 110: reserved 111: reserved reset to 000 23 64-bit address capable rw reset to 1 31:24 reserved ro reset to 00h 6.3.97 message address register ? offset f4h bit function type description 1:0 reserved ro reset to 00 31:2 system specified message address rw reset to 0 6.3.98 message upper address register ? offset f8h bit function type description 31:0 system specified message upper address rw reset to 0
pi7c9x111sl pcie-to-pci reversible bridge page 57 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 6.3.99 message data register ? offset fch bit function type description 15:0 system specified message data rw reset to 0 31:16 reserved ro reset to 0 6.3.100 advance error re porting capability id register ? offset 100h bit function type description 15:0 advance error reporting capability id ro reset to 0001h 6.3.101 advance error repo rting capability version register ? offset 100h bit function type description 19:16 advance error reporting capability version ro reset to 1h 6.3.102 next capability o ffset register ? offset 100h bit function type description 31:20 next capability offset ro next cap ability offset (150h poi nts to vc capability) reset to 150h 6.3.103 uncorrectable error status register ? offset 104h bit function type description 0 training error status rwcs reset to 0 3:1 reserved ro reset to 0 4 data link protocol error status rwcs reset to 0 11:5 reserved ro reset to 0 12 poisoned tlp status rwcs reset to 0 13 flow control protocol error status rwcs reset to 0 14 completion timeout status rwcs reset to 0 15 completer abort status rwcs reset to 0 16 unexpected completion status rwcs reset to 0 17 receiver overflow status rwcs reset to 0 18 malformed tlp status rwcs reset to 0 19 ecrc error status rwcs reset to 0 20 unsupported request error status rwcs reset to 0 31:21 reserved ro reset to 0 6.3.104 uncorrectab le error mask register ? offset 108h bit function type description 0 training error mast rws reset to 0 3:1 reserved ro reset to 0 4 data link protocol error mask rws reset to 0 11:5 reserved ro reset to 0 12 poisoned tlp mask rws reset to 0 13 flow control protocol error mask rws reset to 0
pi7c9x111sl pcie-to-pci reversible bridge page 58 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 bit function type description 14 completion timeout mask rws reset to 0 15 completion abort mask rws reset to 0 16 unexpected completion mask rws reset to 0 17 receiver overflow mask rws reset to 0 18 malformed tlp mask rws reset to 0 19 ecrc error mask rws reset to 0 20 unsupported request error mask rws reset to 0 31:21 reserved ro reset to 0 6.3.105 uncorrectable error severity register ? offset 10ch bit function type description 0 training error severity rws reset to 1 3:1 reserved ro reset to 0 4 data link protocol error severity rws reset to 1 11:5 reserved ro reset to 0 12 poisoned tlp severity rws reset to 0 13 flow control protocol error severity rws reset to 1 14 completion timeout severity rws reset to 0 15 completer abort seve rity rws reset to 0 16 unexpected completion severity rws reset to 0 17 receiver overflow severity rws reset to 1 18 malformed tlp severity rws reset to 1 19 ecrc error severity rws reset to 0 20 unsupported request error severity rws reset to 0 31:21 reserved ro reset to 0 6.3.106 correctable error stat us register ? offset 110h bit function type description 0 receiver error status rwcs reset to 0 5:1 reserved ro reset to 0 6 bad tlp status rwcs reset to 0 7 bad dllp status rwcs reset to 0 8 replay_num rollover status rwcs reset to 0 11:9 reserved ro reset to 0 12 replay timer timeout status rwcs reset to 0 31:13 reserved ro reset to 0 6.3.107 correctable error ma sk register ? offset 114h bit function type description 0 receiver error mask rws reset to 0 5:1 reserved ro reset to 0 6 bad tlp mask rws reset to 0 7 bad dllp mask rws reset to 0 8 replay_num rollover mask rws reset to 0 11:9 reserved ro reset to 0 12 replay timer timeout mask rws reset to 0 31:13 reserved ro reset to 0
pi7c9x111sl pcie-to-pci reversible bridge page 59 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 6.3.108 advanced error capabilities and control register ? offset 118h bit function type description 4:0 first error pointer ros reset to 0h 5 ecrc generation capable ro reset to 1 6 ecrc generation enable rws reset to 0 7 ecrc check capable ro reset to 1 8 ecrc check enable rws reset to 0 31:9 reserved ro reset to 0 6.3.109 header log register 1 ? offset 11ch bit function type description 7:0 header byte 3 ros reset to 0 15:8 header byte 2 ros reset to 0 23:16 header byte 1 ros reset to 0 31:24 header byte 0 ros reset to 0 6.3.110 header log register 2 ? offset 120h bit function type description 7:0 header byte 7 ros reset to 0 15:8 header byte 6 ros reset to 0 23:16 header byte 5 ros reset to 0 31:24 header byte 4 ros reset to 0 6.3.111 header log register 3 ? offset 124h bit function type description 7:0 header byte 11 ros reset to 0 15:8 header byte 10 ros reset to 0 23:16 header byte 9 ros reset to 0 31:24 header byte 8 ros reset to 0 6.3.112 header log register 4 ? offset 128h bit function type description 7:0 header byte 15 ros reset to 0 15:8 header byte 14 ros reset to 0 23:16 header byte 13 ros reset to 0 31:24 header byte 12 ros reset to 0 6.3.113 secondary uncorrectable error status register ? offset 12ch bit function type description 0 target abort on split completion status rwcs reset to 0 1 master abort on split completion status rwcs reset to 0 2 received target abort status rwcs reset to 0 3 received master abort status rwcs reset to 0 4 reserved ro reset to 0 5 unexpected split completion error status rwcs reset to 0
pi7c9x111sl pcie-to-pci reversible bridge page 60 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 bit function type description 6 uncorrectable split completion message data error status rwcs reset to 0 7 uncorrectable data error status rwcs reset to 0 8 uncorrectable attribute error status rwcs reset to 0 9 uncorrectable address error status rwcs reset to 0 10 delayed transaction discard timer expired status rwcs reset to 0 11 perr_l assertion detected status rwcs reset to 0 12 serr_l assertion detected status rwcs reset to 0 13 internal bridge error status rwcs reset to 0 31:14 reserved ro reset to 0 6.3.114 secondary uncorrectable e rror mask register ? offset 130h bit function type description 0 target abort on split completion mask rws reset to 0 1 master abort on split completion mask rws reset to 0 2 received target abort mask rws reset to 0 3 received master abort mask rws reset to 1 4 reserved ro reset to 0 5 unexpected split completion error mask rws reset to 1 6 uncorrectable split completion message data error mask rws reset to 0 7 uncorrectable data error mask rws reset to 1 8 uncorrectable attribute error mask rws reset to 1 9 uncorrectable address error mask rws reset to 1 10 delayed transaction discard timer expired mask rws reset to 1 11 perr_l assertion detected mask rws reset to 0 12 serr_l assertion detected mask rws reset to 1 13 internal bridge error mask rws reset to 0 31:14 reserved ro reset to 0 6.3.115 secondary uncorrectable erro r severity register ? offset 134h bit function type description 0 target abort on split completion severity rws reset to 0 1 master abort on split completion severity rws reset to 0 2 received target abort severity rws reset to 0 3 received master abort severity rws reset to 0 4 reserved ro reset to 0
pi7c9x111sl pcie-to-pci reversible bridge page 61 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 bit function type description 5 unexpected split completion error severity rws reset to 0 6 uncorrectable split completion message data error severity rws reset to 1 7 uncorrectable data error severity rws reset to 0 8 uncorrectable attribute error severity rws reset to 1 9 uncorrectable address error severity rws reset to 1 10 delayed transaction discard timer expired severity rws reset to 0 11 perr_l assertion detected severity rws reset to 0 12 serr_l assertion detected severity rws reset to 1 13 internal bridge error severity rws reset to 0 31:14 reserved ro reset to 0 6.3.116 secondary error capability and control register ? offset 138h bit function type description 4:0 secondary first error pointer row reset to 0 31:5 reserved ro reset to 0 6.3.117 secondary header log re gister ? offset 13ch ? 148h bit function type description 35:0 transaction attribute ros tran saction attribute, cbe [3:0] and ad [31:0] during attribute phase reset to 0 39:36 transaction command lower ros transaction command lower, cbe [3:0] during first address phase reset to 0 43:40 transaction command upper ros transaction command upper, cbe [3 :0] during second address phase of dac transaction reset to 0 63:44 reserved ros reset to 0 95:64 transaction address ros transaction addr ess, ad [31:0] during first address phase reset to 0 127:96 transaction address ros transaction addres s, ad [31:0] during second address phase of dac transaction reset to 0 6.3.118 reserved register ? offset 14ch 6.3.119 vc capability id register ? offset 150h bit function type description 15:0 vc capability id ro reset to 0002h 6.3.120 vc capability version register ? offset 150h
pi7c9x111sl pcie-to-pci reversible bridge page 62 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 bit function type description 19:16 vc capability version ro reset to 1h 6.3.121 next capability o ffset register ? offset 150h bit function type description 31:20 next capability offset ro next capability offset ? th e end of capabilities reset to 0 6.3.122 port vc capability register 1 ? offset 154h bit function type description 2:0 extended vc count ro reset to 0 3 reserved ro reset to 0 6:4 low priority extended vc count ro reset to 0 7 reserved ro reset to 0 9:8 reference clock ro reset to 0 11:10 port arbitration table entry size ro reset to 0 31:12 reserved ro reset to 0 6.3.123 port vc capability register 2 ? offset 158h bit function type description 7:0 vc arbitration capability ro reset to 0 23:8 reserved ro reset to 0 31:24 vc arbitration table offset ro reset to 0 6.3.124 port vc control register ? offset 15ch bit function type description 0 load vc arbitration table ro reset to 0 3:1 vc arbitration select ro reset to 0 15:4 reserved ro reset to 0 6.3.125 port vc status register ? offset 15ch bit function type description 16 vc arbitration table status ro reset to 0 31:17 reserved ro reset to 0 6.3.126 vc0 resource capability register ? offset 160h bit function type description 7:0 port arbitration capability ro reset to 0 13:8 reserved ro reset to 0 14 advanced packet switching ro reset to 0 15 reject snoop transactions ro reset to0 22:16 maximum time slots ro reset to 0 23 reserved ro reset to 0 31:24 port arbitration table offset ro reset to 0 6.3.127 vc0 resource control register ? offset 164h bit function type description
pi7c9x111sl pcie-to-pci reversible bridge page 63 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 bit function type description 0 tc / vc map ro for tc0 reset to 1 7:1 tc / vc map rw for tc7 to tc1 reset to 7fh 15:8 reserved ro reset to 0 16 load port arbitration table ro reset to 0 19:17 port arbitration select ro reset to 0 23:20 reserved ro reset to 0 26:24 vc id ro reset to 0 30:27 reserved ro reset to 0 31 vc enable ro reset to 1 6.3.128 vc0 resource status register ? offset 168h bit function type description 0 port arbitration table 1 ro reset to 0 1 vc0 negotiation pending ro reset to 0 31:2 reserved ro reset to 0 6.3.129 reserved registers ? offset 16ch ? 300h 6.3.130 extra gpi/gpo data and control register ? offset 304h bit function type description 3:0 extra gpo rwc gpo [3:0], write 1 to clear reset to 0 7:4 extra gpo rws gpo [3:0], write 1 to set reset to 0 11:8 extra gpo enable rwc gpo [3 :0] enable, write 1 to clear reset to 0 15:12 extra gpo enable rws gpo [3:0] enable, write 1 to set reset to 0 19:16 extra gpi ro extra gpi [3:0] data register reset to 0 31:20 reserved ro reset to 0 6.3.131 reserved registers ? offset 308h ? 30ch 6.3.132 replay and acknowledge latency timers ? offset 310h bit function type description 11:0 replay timer rw replay timer reset to 0 12 replay timer enable rw replay timer enable reset to 0 15:13 reserved ro reset to 0 29:16 acknowledge latency timer rw acknowledge latency timer reset to 0 30 acknowledge latency timer enable ro acknowledge latency timer enable reset to 0 31 reserved ro reset to 0 6.3.133 reserved registers ? offset 314h ? ffch
pi7c9x111sl pcie-to-pci reversible bridge page 64 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 7 gpio pins and sm bus address gpio[3:0] have been defined for hot-plug usage if msk_in=1. for forward bridge: gpio[0] : pci slot card presence detection input gpio[1] : attenti on button pressed input gpio[2] : power indication output gpio[3] : attention indication output for reverse bridge: gpio[0] : pcie slot card presence detection input gpio[1] : mrl sensor input gpio[3:0] are defined for smbus device id if tm0=1. gpio[3:0] can be further defined to serve other functions in the further generations. with 128qfp package, additional three gp i and three gpo pins can be used wh en external arbiter is selected, and req_l[3:1] and gnt_l[3:1] will be mapped to gpi[2:0] and gpo[2:0] respectively. the address-strapping table of smbus with gpio [3:0] pins is defined in the following table: table 7-1 sm bus device id strapping sm bus address bit sm bus device id address bit [7] = 1 address bit [6] = 1 address bit [5] = 0 address bit [4] = gpio [3] address bit [3] = gpio [2] address bit [2] = gpio [1] address bit [1] = gpio [0] the smbus commands of pi7c9x111sl are provided below: write word protocol (pec disabled): s + slave address[7:1] + 0(wr) + a + 0000_1000 + a + bus number[7:0] + a + device/function + a + p s + slave address[7:1] + 0(wr) + a + 0000_1000 + a + reg number[7:0] + a + reg number[15:8] + a + p s + slave address[7:1] + 0(wr) + a + 0000_1000 + a + data[7:0] + a + data[15:8] + a + p read word protocol (pec disabled): s + slave address[7:1] + 0(wr) + a + 0000_1000 + a + bus number[7:0] + a + device/function + a + p s + slave address[7:1] + 0(wr) + a + 0000_1000 + a + reg number[7:0] + a + reg number[15:8] + a + p s + slave address[7:1] + 0(wr) + a + 0000_1000 + a + sr + slave address[7:1] + 1(rd) + a + data[7:0] + a + data[15:8] + n + p where bus number and device/function filed have to be 0x00
pi7c9x111sl pcie-to-pci reversible bridge page 65 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 8 clock scheme pci express interface: pi7c9x111sl requires 100mhz differential clock inputs through the pins of refclkp and refclkn. when the clock applied to pi7c9x111slb and other end of the pcie link are from the same clock source, the msk_in input should be kept unchanged before and after reset (perst_l for forward bridge or reset_l for reverse bridge). otherwise, the msk_in input should be different before and after the reset. pci interface: pi7c9x111sl generates four clock outputs, from either external clock input (1mhz to 66mhz) at clkin or internal clock generator: pi7c9x111sl can use configuration control to enable or disable the secondary clock output: clkout[3:0]. pi7c9x111sl used either internally feedbacked clock from clkout[0] or external clock input applied at clkout[0], for internal secondary interface logic. for using internal clock source, the internal clock generator needs to be enabled with clkin driven high or low. clkin and m66en signals become the selection for pci frequency at 50mhz/25mhz or 66mhz/33mhz. frequency of pci clkout with internal clock source: clkin m66en pci clock 0 0 33mhz 0 1 66mhz 1 0 25mhz 1 1 50mhz the pi7c9x111sl pci clock outputs, clkout [3:0], can be enabled or disabled through the configuration register. pi7c9x111sl supports three different implementation of pci clock. ? internal clock generator, and internal clock buffering. o internal feedback o external feedback ? external clock source, and internal clock buffering. o internal feedback o external feedback ? external clock source, and external clock buffering.
pi7c9x111sl pcie-to-pci reversible bridge page 66 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 topology of internal clock generator and internal clock buffering: 1. internal feedback: 2. external feedback: topology of external clock source and internal clock buffering: 1. internal feedback: 2. external feedback: pi7c9x111sl clock generator pci device clkout0 pci device clkout3 pci device clkout2 pci device clkout1 clkin pi7c9x111sl clock generator clkout0 pci device clkout3 pci device clkout2 clkout1 clkin n ote: feedback source could be from an y clkout pi7c9x111sl clock generator pci device clkout0 pci device clkout3 pci device clkout2 pci device clkout1 clkin clock source
pi7c9x111sl pcie-to-pci reversible bridge page 67 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 in this configuration, user simply co nnects the external clock source to clkin pin. and user needs to make sure the clock is preset (toggling) before the fundamental reset de-asserted (e.g. perst_l when forward mode, and reset_l when reverse mode). in this mode, the frequency is the same as the input clock source. topology of external clock source and external clock buffering: in this configuration, user simply co nnects the external clock from the clock buffers to clkout0. and user needs to make sure the clock is preset (toggling) before th e fundamental reset de-asserted (e.g. perst_l when forward mode, and reset_l when reverse mode). 9 interrupts pi7c9x111sl clock generator pci device clkout3 pci device clkout2 clkin clock source clkout0 clkout1 n ote: feedback source could be from an y clkout pi7c9x111sl clock generator pci device clkout0 clkout3 pci device clkout2 pci device clkout1 clkin n ot used external clock buffers n ot used clock source
pi7c9x111sl pcie-to-pci reversible bridge page 68 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 pi7c9x111sl supports interrupt message packets on pcie side. pi7c9x111sl supports pci interrupt (inta, b, c, d) pins or msi (message signaled interrupts) on pci side. pci interrupts and msi are mutually exclusive. in order words, if msi is enabled, pci interrupts will be disabled. pi7c9x111sl support 64-bit addressing msi. in reverse bridge mode, pi7c9x111sl maps the interrupt message packets to pci interrupt pins or msi if msi is enable (see configuration regist er bit [16] of offset f0h). in forward bridge mode, pi7c9x111sl maps the pci interrupts pins or msi if enable on pci side to interrupt message packets on pcie side. there are eight interrupt me ssage packets. they are assert_inta, assert_intb, assert_intc, assert_intd, deassert_inta, deassert_intb, deassert_intc, and dea ssert_intd. these eight interrupt messages are mapped to the four pci interrupts (inta, intb, intc, and intd). see table 9-1 for interrupt mapping information in reverse bridge mode. pi7c9x111sl tracks the pci interrupt (inta, intb, intc, and intd) pins and maps them to the eight interrupt messages. see table 9-2 for interrupt mapping information in forward bridge mode. table 9-1 pcie interrupt message to pci in terrupt mapping in reverse bridge mode pcie interrupt messages (from sources of interrupt) pci interrupts (to host controller) inta message inta intb message intb intc message intc intd message intd table 9-2 pci interrupt to pc ie interrupt message mapping in forward bridge mode pci interrupts (from sources of interrupts) pcie interrupt message packets (to host controller) inta inta message intb intb message intc intc message intd intd message 10 eeprom (i2c) interface and system management bus 10.1 eeprom (i2c) interface pi7c9x111sl supports eeprom interface through i2c bus. in eeprom interface, pin 3 is the eeprom clock (scl) and pin 4 is the eeprom data (sdl). tm1 and tm0 are strapped accor dingly to select eeprom interface or system management bus. eeprom (i2c) interface is enabled with tm1=0 and tm0=0. when eeprom interface is selected , scl is an output. scl is the i2c bus clock to the i2c device. in addition, sdl is a bi- directional signal for se nding and receiving data. 10.2 system management bus pi7c9x111sl supports sm bus protocol if tm1=0 and tm0=1. in addition, smbclk (pin 3) and smbdat (pin 4) are utilized as the clock and data pins respectively for the sm bus.
pi7c9x111sl pcie-to-pci reversible bridge page 69 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 when sm bus interface is selected, smbclk pin is an i nput for the clock of smbus and smbdat pin is an open drain buffer that requires external pull-up resistor for proper operation. the sm bus commands of pi7c9x111sl are provided below: write word protocol (pec disabled): s + slave address[7:1] + 0(wr) + a + 0000_1000 + a + bus number[7:0] + a + device/function + a + p s + slave address[7:1] + 0(wr) + a + 0000_1000 + a + reg number[7:0] + a + reg number[15:8] + a + p s + slave address[7:1] + 0(wr) + a + 0000_1000 + a + data[7:0] + a + data[15:8] + a + p read word protocol (pec disabled): s + slave address[7:1] + 0(wr) + a + 0000_1000 + a + bus number[7:0] + a + device/function + a + p s + slave address[7:1] + 0(wr) + a + 0000_1000 + a + reg number[7:0] + a + reg number[15:8] + a + p s + slave address[7:1] + 0(wr) + a + 0000_1000 + a + sr + slave address[7:1] + 1(rd) + a + data[7:0] + a + data[15:8] + n + p where bus number and device/function filed have to be 0x00. for additional info on smbus programming, please refer to section 7 of datasheets. 10.3 eeprom autoload configuration eeprom byte addresses cfg offset description 00-01h eeprom signa ture: autoload will only pr oceed if it reads a value of 1516h on the first word loaded. 02h region enable: enables or di sables certain regions of pci configuration space from being loaded from the eeprom. bit 0: reserved bit 4-1: 0000=stop autoload at offset 0bh: group 1 0001=stop autoload at offset 67h: group 2 0011=stop autoload at offset afh: group 3 0111=stop autoload at offset d7h: group 4 other combinations are undefined bit 7-5: reserved 03h enable miscellaneous functions: (for transparent mode only) bit 0: isa enable control bit write protect: when this bit is set, 9x111 will change the bit 2 of 3eh into ro, and isa enable feature will not be available. 04-05h 00-01h vendor id 06-07h 02-03h device id 08h 08h revision id 09h 09h class code: low bytes of class code register 0a-0bh 0a-0bh class code highe r bytes: upper bytes of class code register 0ch 34h capability pointer 0d-0eh 40-41h pci data prefetching control 0f-10h 42-43h chip control 0 11-14h 48-4bh arbiter mode/enable/priority 15-18h 68-6bh pcie transmitter/receiver control 19-1ah 81-82h pcix capability 1bh 108h uncorrectable error mask register 1c-1eh 91-93h power management capability 1f-21h a1-a3h si capability 22-25h a4-a7h seconda ry clock and clkrun control 26-29h a8-abh ssid/ssvid capability 2a-2dh ac-afh ssid/ssvid
pi7c9x111sl pcie-to-pci reversible bridge page 70 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 eeprom byte addresses cfg offset description 2e-30h b1-b3h pci express capabilities 31-34h b4-b7h device capabilities 35-38h bc-bfh link capabilities 39-3ch c4-c7h slot capabilities 3d-40h cc-cfh xpip configuration register 0 41-44h d0-d3h xpip configuration register 1 45-48h d4-d7h xpip configuration register 2 49-4ah d9-dah vpd capability 4b-4ch f1-f2h msi capability 4dh 100h advance error reporting capability 4e-4fh 109-10ah uncorrectable error mask register 50-51h e0-e1h extended cfg access address 52-55h e4-e7h extended cfg access data 56-57h e0-e1h extended cfg access address 58-5bh e4-e7h extended cfg access data 5c-5dh e0_e1h extended cfg access address 5e-61h e4-e7h extended cfg access data 62-63h e0_e1h extended cfg access address 64-67h e4-e7h extended cfg access data 68-77h reserved 79-7bh 79-7bh gpio data and control 7c-7dh reserved 7eh 86h pcix bridge status 7f-82h 88-8bh upstream split transaction 83-86h 8c-8fh downstream split transaction 87-8ah 94-97h pm control and status 8b-8eh b4-b7h device capabilities 8f-91h b8-bah device control/status 92h reserved 93h c0h link control/status 94h reserved 95-96h c2-c3h link control/status 97-98h c8-c9h slot control/status 99-9ah 3c-3dh interrupt control 9b-9eh dc-dfh vpd data 9f-a2h f4-f7h message address a3-a6h f8-fbh message upper address a7-a8h fc-fdh message data a9h reserved aa-abh 7c-7dh sec interrupt control ac-adh 310-311h replay timer ae-afh 312-313h ack latency timer b0-b3h 04-07h command/status b4-b6h 0c-0eh cacheline/primary latency timer/header type b7h reserved b8-bbh 18-1bh bus number/secondary latency timer bc-bfh 1c-1fh i/o base/limit / s econdary status c0-c3h 20-23h memory base/limit c4-c7h 24-27h prefetch memory base/limit c8-cbh 28-2bh prefetch upper 32 base cc-cfh 2c-2fh prefetch upper 32 limit d0-d3h 30-33h i/o upper 16 base/limit d4-d5h reserved d6-d7h 3e-3fh bridge control d8-ffh reserved 11 hot plug operation
pi7c9x111sl pcie-to-pci reversible bridge page 71 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 pi7c9x111sl is not equipped with standard hot-plug controller (shpc) integrated. however, pi7c9x111sl supports hot-plug signaling messages and registers to simplify the implementation of hot-plug system. using pi7c9x111sl on motherboard: ? pi7c9x111sl supports hot-plug on pci bus if forward bridging is selected (revrsb=0). ? pi7c9x111sl supports hot-plug function on pci express bus when reverse bridge mode is selected (revrsb=1). using pi7c9x111sl on add-in card: ? pi7c9x111sl supports hot-plug on pci express bus in forward bridge mode. hot-plug messages will be generated by pi7c9x111sl based on the add-in card conditions. ? pi7c9x111sl supports hot-plug function on pci bus when reverse bridge mode is selected. pi7c9x111sl will tri-state the pci bus when reset is asserted. also, pi7c9x111sl will de-assert inta_l if reset is asserted. th e state machine of pi7c9x111sl pci bus interface will remain idle if the reset is asserted. after re set is de-asserted, pi7c9x111sl will remain in idle state until an address phase containing a valid address for pi7c9x111sl or its downstream devices. ? pi7c9x111sl expects the refclk signal will be provid ed to its upstream pci express port prior to the de-assertion of reset. the downstream pci port of pi7c9x111sl supports a range of frequency up to 66mhz. ? pi7c9x111sl also supports subsystem vendor and subsystem id. pi7c9x111 sl will ignore target response while the bus is idle. prsnt1# and prsnt2# are not implemented on both pi7c9x111sl. the use of these two signals is mandatory on an add-in card in order to support hot-plug. 12 reset scheme pi7c9x111sl requires the fundamental reset (perst_l) input for internal logic when it is set as forward bridge mode. pi7c9x111sl requires the pci reset (reset_l) input when it is set as reverse bridge mode. also, pi7c9x111sl has a power-on-reset (por) circuit to detect vddcaux power supply for auxiliary logic control. ? cold reset: a cold reset is a fundamental or power-on reset that occu rs right after the power is a pplied to pi7c9x111sl (during initial power up). see section 7.1.1 of pci express to pci bridge specification, revision 1.0 for details. ? warm reset: a warm reset is a reset that triggered by the hardware without removing and re-applying the power sources to pi7c9x111sl. ? hot reset: a hot reset is a reset that used an in-band mechanism for propagating reset across a pcie link to pi7c9x111sl. pi7c9x111sl will enter to training control reset when it receives two consecutive ts1 or ts2 order-sets with reset bit set. ? dl_down reset: if the pcie link goes down, the transaction and data link layer will enter dl_down status. pi7c9x111sl discards all transactions and returns all logic and registers to initial state except the sticky registers.
pi7c9x111sl pcie-to-pci reversible bridge page 72 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 upon receiving reset (cold, warm, ho t, or dl_down) on pcie interface, pi7c9x111sl will generate pci reset (reset_l) to the downstream devices on the pci bus in forward bridge mode. the pci reset de-assertion follows the de-assertion of the reset received fr om pcie interface. the reset bit of bridge control register may be set depending on the application. pi7c9x 111sl will tolerant to receive and pro cess skip order-sets at an average interval between 1180 to 1538 symbol times. pi7c9x111sl does not keep pci reset active when vd33 power is off even though vaux (3.3v) is supported. it is recomm ended to add a weak pull-down resistor on its application board to ensure pci reset is low when vd33 power is off (see section 7.3.2 of pci bus power management specification revision 1.1). in reverse bridge mode, pi7c9x111sl generates fundamental reset (perst_l) and then 1024 ts1 order-sets with reset bit set when pci reset (reset_l) is asserted to pi7c9x111sl. pi7c9x111sl has scheduling skip order-set for insertion at an interval between 1180 and 1538 symbol times. pi7c9x111sl transmits one electrical idle order-set and enters to electrical idle. 13 ieee 1149.1 compat ible jtag controller an ieee 1149.1 compatible test access port (tap) contro ller and associated tap pins are provided to support boundary scan in pi7c9x111sl for board-level continuity test and diagnostics. the tap pins assigned are tck, tdi, tdo, tms and trst_l. all digital input, output, input/output pins are tested except tap pins. the ieee 1149.1 test logic consists of a tap controller, an instruction register, and a group of test data registers including bypass and boundary scan registers. the tap controller is a synchronous 16-state machine driven by the test clock (tck) and the test mode select (tms) pins. an independent power on reset circuit is provided to ensure the machine is in test_logic_reset state at po wer-up. the jtag signal lin es are not active when the pci resource is opera ting pci bus cycles. 13.1 instruction register pi7c9x111sl implements a 5-bit instruction register to control the operation of the jtag logic. the defined instruction codes are shown in table 14 -1. those bit combinations that are not listed are equivalent to the bypass (11111) instruction: table 13-1 instruction register codes instruction operation code (binary) register selected operation extest 00000 boundary scan drives / receives off-chip test data sample 00001 boundary scan samples inputs / pre-loads outputs highz 00101 bypass tri-states output and i/o pins except tdo pin clamp 00100 bypass drives pins from boundary-scan register and selects bypass register for shifts idcode 01100 device id accesses the device id register, to read manufacturer id, part number, and version number bypass 11111 bypass selected bypass register int_scan 00010 internal scan scan test mem_bist 01010 memory bist memory bist test 13.2 bypass register
pi7c9x111sl pcie-to-pci reversible bridge page 73 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 the required bypass register (one-bit shift register) provid es the shortest path between tdi and tdo when a bypass instruction is in effect. this allows rapid movement of test data to and from other components on the board. this path can be selected when no test operation is being performed on the pi7c9x111sl. 13.3 device id register this register identifies pericom as the manufacturer of the device and details the part number and revision number for the device. table 13-2 jtag device id register bit type value description 31:28 ro 01h version number 27:12 ro e110h last 4 digits (hex) of the die part number 11:1 ro 23fh pericom identifier assigned by jedec 0 ro 1b fixed bit equal to 1?b1 13.4 boundary scan register the boundary scan register has a set of serial shift-register cells. a chain of boundary scan cells is formed by connected the internal signal of the pi7c9x111sl package pins. the vdd, vss, and jtag pins are not in the boundary scan chain. the input to the shift register is tdi and the output from the shift register is tdo. there are 4 different types of boundary scan cells, based on the function of each signal pin. the boundary scan register cells are dedi cated logic and do not have any system function. data may be loaded into the boundary scan register master cells from the device input pins and output pin-drivers in parallel by the mandatory sample and extest instructions. parallel lo ading takes place on the rising edge of tck. 13.5 jtag boundary sc an register order 14 power management pi7c9x111sl supports d0, d3-hot, d3-cold power states. d1 and d2 states are not supported. the pci express physical link layer of the pi7c9x111sl device supports the pci express link power management with l0, l0s, l1, l2/l3 ready and l3 power states. for the pci port of pi7c9x111sl, it supports the standard pci power management states with b0, b1, b2 and b3. during d3-hot state, the main power supplies of vddp, vddc, and vd33 can be turned off to save power while keeping the vddaux, vd dcaux, and vaux with the auxiliary power supplies to maintain all necessary information to be restored to the full power d0 state. pi7c9x111sl has been designed to have sticky registers that are powered by auxiliary power supplies. pme_l pin allows pci devices to request power management state changes. along with the operating system and application software, pc i devices can achieve optimum power saving by using pme_l in forward bridge mode. pi7c9x111sl converts pme_l signal information to power management messages to the upstream switches or root complex. in reverse bridge mode, pi7c9x111sl converts the power management event messages from pcie devices to the pme_l signal and continues to request power management state change to the host bridge.
pi7c9x111sl pcie-to-pci reversible bridge page 74 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 pi7c9x111sl also supports aspm (active state power management) to facilitate the link power saving. pi7c9x111sl supports beacon generation but does not support wake# signal during power management.
pi7c9x111sl pcie-to-pci reversible bridge page 75 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 15 electrical and timing specifications 15.1 absolute maximum ratings table 15-1 absolute maximum ratings (above which the useful life may be impair ed. for user guidelines, not tested.) storage temperature -65 o c to 150 o c ambient temperature with power applied -40 o c to 85 o c pci express supply voltage to ground potential (vdda, vddp, vddc, vddaux, and vddcaux) -0.3v to 3.0v pci supply voltage to ground potential (vd33 and vaux) -0.3v to 3.6v dc input voltage for pci express signals -0.3v to 3.0v dc input voltage for pci signals -0.5v to 5.75v note: stresses greater than those listed under m aximum ratings may cause permanent dama ge to the device. this is a stress rating only and functional operation of the device at these or any conditions above t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condi tions for extended periods of time may affect reliability. 15.2 dc specifications table 15-2 dc electrical characteristics power pins min. typ. max. vdda 0.9v 1.0v 1.1v vddp 09.v 1.0v 1.1v vddc 09.v 1.0v 1.1v vddaux 09.v 1.0v 1.1v vddcaux 09.v 1.0v 1.1v vtt 1.0v 1.5v 1.8v vd33 3.0v 3.3v 3.6v vaux 3.0v 3.3v 3.6v vdda: analog power supply for pci express interface vddp: digital power supply for pci express interface vddaux: digital auxiliary power supply for pci express interface vtt: termination power suppl y for pci express interface vddc: digital power power supply for the core vddcaux: digital auxiliary power supply for the core vd33: digital power supply for pci interface vaux: digital auxiliary powe r supply for pci interface in order to support auxiliary power management fully, it is recommended to have vddp and vddaux separated. by the same token, vd33/vddc and vaux/vddcaux need to be separate d for auxiliary power management support. however, if auxiliary power management is not required, vd33 and vddc can be connected to vaux and vddcaux respectively. the typical power consumption of pi7c9x111sl is less than 0.45 watt.
pi7c9x111sl pcie-to-pci reversible bridge page 76 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 pi7c9x111sl is capable of sustaining 2000v human body model for the esd protection without any damages. 15.3 ac specifications table 15-3 pci bus timing parameters 66 mhz 33 mhz symbol parameter min max min max units tsu input setup time to clk ? bused signals 1,2,3 3 - 7 - tsu (ptp) input setup time to clk ? point-to-point 1,2,3 5 - 10, 12 4 - th input signal hold time from clk 1,2 0 - 0 - tval clk to signal valid delay ? bused signals 1,2,3 2 6 2 11 tval (ptp) clk to signal valid delay ? point-to-point 1,2,3 2 6 2 12 ton float to active delay 1,2 2 - 2 - toff active to float delay 1,2 - 14 - 28 ns 1. see figure 16 ?1 pci signal timing measurement conditions. 2. all pci interface signals are synchronized to clkout0. 3. point-to-point signals are req_l [7:0], gnt_l [7:0], loo, and enum_l. bused signals are ad, cbe, par, perr_l, serr_l, frame_l, irdy_l , trdy_l, lock_l, stop_l and idsel. 4. req_l signals have a setup of 10ns and gnt_l signals have a setup of 12ns. figure 15-1 pci signal timing conditions
pi7c9x111sl pcie-to-pci reversible bridge page 77 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 16 package information the package of pi7c9x111sl comes in 14mm x 14mm lqfp (128 pin) package. the pin pitch is 0.4mm. this package also includes an exposed ground on the bottom su rface of the package. pericom highly recommends implementing this exposed ground pad on any customer boards. the following are the package information and mechanical dimension: figure 16-1 package outline drawing
pi7c9x111sl pcie-to-pci reversible bridge page 78 of 78 pericom semiconductor - confidential feb, 2010, revision 1.5 17 ordering information part number pin ? package pb-free & green temperature range PI7C9X111SLBFDE 128 ? lqfp (exposed ground pad) yes -40c to +85c notes:

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